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Signed-off-by: Sean Cross <[email protected]>
1 parent fb65ae5 commit eaa4f24

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8 files changed

+211
-59
lines changed

8 files changed

+211
-59
lines changed

‎src/command.c‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,7 @@ const command_s cmd_list[] = {
117117
{"halt_timeout", cmd_halt_timeout, "Timeout to wait until Cortex-M is halted: [TIMEOUT, default 2000ms]"},
118118
{"connect_rst", cmd_connect_reset, "Configure connect under reset: [enable|disable]"},
119119
{"reset", cmd_reset, "Pulse the nRST line - disconnects target: [PULSE_LEN, default 0ms]"},
120+
{"reset_halt", cmd_reset, "Reset the target and halt at the first instruction"},
120121
{"tdi_low_reset", cmd_tdi_low_reset,
121122
"Pulse nRST with TDI set low to attempt to wake certain targets up (eg LPC82x)"},
122123
#ifdef PLATFORM_HAS_POWER_SWITCH
@@ -573,6 +574,19 @@ static bool cmd_halt_timeout(target_s *target, int argc, const char **argv)
573574
return true;
574575
}
575576

577+
static bool cmd_reset_halt(target_s *target, int argc, const char **argv)
578+
{
579+
(void)target;
580+
uint32_t pulse_len_ms = 0;
581+
if (argc > 1)
582+
pulse_len_ms = strtoul(argv[1], NULL, 0);
583+
target_list_free();
584+
platform_nrst_set_val(true);
585+
platform_delay(pulse_len_ms);
586+
platform_nrst_set_val(false);
587+
return true;
588+
}
589+
576590
static bool cmd_reset(target_s *target, int argc, const char **argv)
577591
{
578592
(void)target;

‎src/include/target.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,8 +72,10 @@ void target_detach(target_s *target);
7272
/* Memory access functions */
7373
bool target_mem_map(target_s *target, char *buf, size_t len);
7474
bool target_mem32_read(target_s *target, void *dest, target_addr_t src, size_t len);
75+
bool target_mem32_read_unswapped(target_s *const target, void *const dest, const target_addr_t src, const size_t len);
7576
bool target_mem64_read(target_s *target, void *dest, target_addr64_t src, size_t len);
7677
bool target_mem32_write(target_s *target, target_addr_t dest, const void *src, size_t len);
78+
bool target_mem32_write_unswapped(target_s *target, target_addr_t dest, const void *src, size_t len);
7779
bool target_mem64_write(target_s *target, target_addr64_t dest, const void *src, size_t len);
7880
bool target_mem_access_needs_halt(target_s *target);
7981
/* Flash memory access functions */

‎src/platforms/hosted/rtt_if.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,12 @@ int rtt_if_init(void)
5757
ttystate.c_lflag &= ~ECHO;
5858
ttystate.c_cc[VMIN] = 1;
5959
tcsetattr(STDIN_FILENO, TCSANOW, &ttystate);
60+
61+
// tcgetattr(STDOUT_FILENO, &saved_ttyoutstate);
62+
// tcgetattr(STDOUT_FILENO, &ttystate);
63+
// ttystate.c_lflag &= ~(ECHO | ICANON);
64+
// tcsetattr(STDOUT_FILENO, TCSANOW, &ttystate);
65+
6066
int flags = fcntl(0, F_GETFL, 0);
6167
fcntl(0, F_SETFL, flags | O_NONBLOCK);
6268
return 0;

‎src/rtt.c‎

Lines changed: 49 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -121,6 +121,7 @@ static char xmit_buf[RTT_UP_BUF_SIZE];
121121
* [Algo] Rolling hash; Rabin-Karp string search
122122
* - 0: https://yurichev.com/news/20210205_rolling_hash/
123123
*/
124+
124125
static uint32_t fast_search(target_s *const cur_target, const uint32_t ram_start, const uint32_t ram_end)
125126
{
126127
static const uint32_t hash_len = 16;
@@ -140,12 +141,17 @@ static uint32_t fast_search(target_s *const cur_target, const uint32_t ram_start
140141
gdb_outf("rtt: read fail at 0x%" PRIx32 "\r\n", addr);
141142
return 0;
142143
}
144+
fprintf(stderr, "RTT @ 0x%08x: ", addr);
143145
for (uint32_t i = 0; i < buf_siz; i++) {
146+
fprintf(stderr, " %02x", srch_buf[i + hash_len]);
144147
hash = (hash + q - remainder * srch_buf[i] % q) % q;
145148
hash = ((hash << 8U) + srch_buf[i + hash_len]) % q;
146-
if (pattern == hash)
149+
if (pattern == hash) {
150+
fprintf(stderr, "\n");
147151
return addr + i - hash_len + 1U;
152+
}
148153
}
154+
fprintf(stderr, "\n");
149155
}
150156
/* no match */
151157
return 0;
@@ -209,7 +215,7 @@ static void find_rtt(target_s *const cur_target)
209215
DEBUG_INFO("rtt: match at 0x%" PRIx32 "\n", rtt_cbaddr);
210216
/* read number of rtt up and down channels from target */
211217
uint32_t num_buf[2];
212-
if (target_mem32_read(cur_target, num_buf, rtt_cbaddr + 16U, sizeof(num_buf)))
218+
if (target_mem32_read_unswapped(cur_target, num_buf, rtt_cbaddr + 16U, sizeof(num_buf)))
213219
return;
214220
rtt_num_up_chan = num_buf[0];
215221
if (rtt_num_up_chan > MAX_RTT_CHAN)
@@ -233,6 +239,10 @@ static void find_rtt(target_s *const cur_target)
233239
/* clear channel data */
234240
memset(rtt_channel, 0, sizeof rtt_channel);
235241

242+
/* save first 24 bytes of control block */
243+
if (target_mem32_read_unswapped(cur_target, saved_cblock_header, rtt_cbaddr, sizeof(saved_cblock_header)))
244+
return;
245+
236246
/* auto channel: enable output channel 0, channel 1 and first input channel */
237247
if (rtt_auto_channel) {
238248
for (uint32_t i = 0; i < MAX_RTT_CHAN; i++)
@@ -243,12 +253,9 @@ static void find_rtt(target_s *const cur_target)
243253
rtt_channel_enabled[rtt_num_up_chan] = true;
244254
}
245255

246-
/* save first 24 bytes of control block */
247-
if (target_mem32_read(cur_target, saved_cblock_header, rtt_cbaddr, sizeof(saved_cblock_header)))
248-
return;
249256

250257
rtt_found = true;
251-
DEBUG_INFO("rtt found\n");
258+
DEBUG_INFO("rtt found -- %d up channels and %d down channels\n", num_buf[0], num_buf[1]);
252259
}
253260
}
254261

@@ -276,8 +283,10 @@ static rtt_retval_e read_rtt(target_s *const cur_target, const uint32_t i)
276283
if (cur_target == NULL || rtt_channel[i].buf_addr == 0 || rtt_channel[i].buf_size == 0)
277284
return RTT_IDLE;
278285

279-
if (rtt_channel[i].head >= rtt_channel[i].buf_size || rtt_channel[i].tail >= rtt_channel[i].buf_size)
286+
if (rtt_channel[i].head >= rtt_channel[i].buf_size || rtt_channel[i].tail >= rtt_channel[i].buf_size) {
287+
DEBUG_TARGET("write head: %d buf_size: %d tail: %d\n", rtt_channel[i].head, rtt_channel[i].buf_size, rtt_channel[i].tail);
280288
return RTT_ERR;
289+
}
281290

282291
/* write recv_buf to target rtt 'down' buf */
283292
while (true) {
@@ -287,16 +296,18 @@ static rtt_retval_e read_rtt(target_s *const cur_target, const uint32_t i)
287296
const int ch = rtt_getchar(channel);
288297
if (ch == -1)
289298
break;
290-
if (target_mem32_write(cur_target, rtt_channel[i].buf_addr + rtt_channel[i].head, &ch, 1))
299+
if (target_mem32_write_unswapped(cur_target, rtt_channel[i].buf_addr + rtt_channel[i].head, &ch, 1))
291300
return RTT_ERR;
292301
/* advance head pointer */
293302
rtt_channel[i].head = next_head;
294303
}
295304

296305
/* update head of target 'down' buffer */
297306
const uint32_t head_addr = rtt_cbaddr + 24U + i * 24U + 12U;
298-
if (target_mem32_write(cur_target, head_addr, &rtt_channel[i].head, sizeof(rtt_channel[i].head)))
307+
if (target_mem32_write_unswapped(cur_target, head_addr, &rtt_channel[i].head, sizeof(rtt_channel[i].head))) {
308+
DEBUG_TARGET("Again with the write failure\n");
299309
return RTT_ERR;
310+
}
300311
return RTT_OK;
301312
}
302313

@@ -363,7 +374,7 @@ static rtt_retval_e print_rtt(target_s *const cur_target, const uint32_t i)
363374

364375
/* update tail of target 'up' buffer */
365376
const uint32_t tail_addr = rtt_cbaddr + 24U + i * 24U + 16U;
366-
if (target_mem32_write(cur_target, tail_addr, &rtt_channel[i].tail, sizeof(rtt_channel[i].tail)))
377+
if (target_mem32_write_unswapped(cur_target, tail_addr, &rtt_channel[i].tail, sizeof(rtt_channel[i].tail)))
367378
return RTT_ERR;
368379

369380
/* write buffer to usb */
@@ -413,9 +424,22 @@ void poll_rtt(target_s *const cur_target)
413424
if (rtt_found) {
414425
uint32_t cblock_header[6]; // first 24 bytes of control block
415426
/* check control block not changed or corrupted */
416-
if (target_mem32_read(cur_target, cblock_header, rtt_cbaddr, sizeof(cblock_header)) ||
417-
memcmp(saved_cblock_header, cblock_header, sizeof(cblock_header)) != 0)
427+
if (target_mem32_read_unswapped(cur_target, cblock_header, rtt_cbaddr, sizeof(cblock_header)) ||
428+
memcmp(saved_cblock_header, cblock_header, sizeof(cblock_header)) != 0) {
429+
fprintf(stderr, "Read %lu blocks from 0x%08x and it's different\n", sizeof(cblock_header), rtt_cbaddr);
430+
unsigned int i;
431+
fprintf(stderr, "saved: ");
432+
for (i = 0; i < sizeof(cblock_header)/4; i++) {
433+
fprintf(stderr, " %08x", saved_cblock_header[i]);
434+
}
435+
fprintf(stderr, "\n");
436+
fprintf(stderr, "found: ");
437+
for (i = 0; i < sizeof(cblock_header)/4; i++) {
438+
fprintf(stderr, " %08x", cblock_header[i]);
439+
}
440+
fprintf(stderr, "\n");
418441
rtt_found = false; // force searching control block next poll_rtt()
442+
}
419443
}
420444

421445
bool rtt_err = false;
@@ -424,12 +448,24 @@ void poll_rtt(target_s *const cur_target)
424448
if (rtt_found && rtt_cbaddr) {
425449
/* copy control block from target */
426450
uint32_t rtt_cblock_size = sizeof(rtt_channel[0]) * (rtt_num_up_chan + rtt_num_down_chan);
427-
if (target_mem32_read(cur_target, rtt_channel, rtt_cbaddr + 24U, rtt_cblock_size)) {
451+
if (target_mem32_read_unswapped(cur_target, rtt_channel, rtt_cbaddr + 24U, rtt_cblock_size)) {
428452
gdb_outf("rtt: read fail at 0x%" PRIx32 "\r\n", rtt_cbaddr + 24U);
429453
rtt_err = true;
430454
} else {
431455
for (uint32_t i = 0; i < rtt_num_up_chan + rtt_num_down_chan; i++) {
432456
if (rtt_channel_enabled[i]) {
457+
// fprintf(stderr, "RTT Channel %d -- name @ %08x buf @ %08x buf_size: %08x (%d) Head: %08x (%d) Tail: %08x (%d), flag: %08x\n",
458+
// i,
459+
// rtt_channel[i].name_addr,
460+
// rtt_channel[i].buf_addr,
461+
// rtt_channel[i].buf_size,
462+
// rtt_channel[i].buf_size,
463+
// rtt_channel[i].head,
464+
// rtt_channel[i].head,
465+
// rtt_channel[i].tail,
466+
// rtt_channel[i].tail,
467+
// rtt_channel[i].flag
468+
// );
433469
rtt_retval_e result;
434470
if (i < rtt_num_up_chan)
435471
result = print_rtt(cur_target, i); /* rtt from target to host */

‎src/target/cortexar.c‎

Lines changed: 32 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,8 @@ typedef struct cortexar_priv {
7070
uint32_t spsr[5U];
7171
uint64_t d[16U];
7272
uint32_t fpcsr;
73+
uint32_t dfsr;
74+
uint32_t dfar;
7375
} core_regs;
7476

7577
/* Fault status/address cache */
@@ -701,7 +703,6 @@ static target_addr_t cortexar_virt_to_phys(target_s *const target, const target_
701703
static bool cortexar_oslock_unlock(target_s *const target)
702704
{
703705
const uint32_t lock_status = cortex_dbg_read32(target, CORTEXAR_DBG_OSLSR);
704-
DEBUG_TARGET("%s: OS lock status: %08" PRIx32 "\n", __func__, lock_status);
705706
/* Check if the lock is implemented, then if it is, if it's set */
706707
if (((lock_status & CORTEXAR_DBG_OSLSR_OS_LOCK_MODEL) == CORTEXAR_DBG_OSLSR_OS_LOCK_MODEL_FULL ||
707708
(lock_status & CORTEXAR_DBG_OSLSR_OS_LOCK_MODEL) == CORTEXAR_DBG_OSLSR_OS_LOCK_MODEL_PARTIAL) &&
@@ -1022,7 +1023,8 @@ static inline uint32_t cortexar_endian_dp_read(target_s *const target, const uin
10221023
{
10231024
cortexar_priv_s *const priv = (cortexar_priv_s *)target->priv;
10241025
uint32_t value = adiv5_dp_read(priv->base.ap->dp, addr);
1025-
if (target->target_options & TOPT_FLAVOUR_BE) {
1026+
extern bool skip_swap;
1027+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap) {
10261028
uint8_t tmp_value[4];
10271029
// The instruction run gave us back a value that we interpreted as little endian, however
10281030
write_le4(tmp_value, 0, value);
@@ -1035,8 +1037,9 @@ static inline uint32_t cortexar_endian_dp_read(target_s *const target, const uin
10351037
static inline void cortexar_endian_dp_write(target_s *const target, const uint16_t addr, uint32_t value)
10361038
{
10371039
cortexar_priv_s *const priv = (cortexar_priv_s *)target->priv;
1040+
extern bool skip_swap;
10381041

1039-
if (target->target_options & TOPT_FLAVOUR_BE) {
1042+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap) {
10401043
uint8_t tmp_value[4];
10411044
// The instruction run gave us back a value that we interpreted as little endian, however
10421045
write_le4(tmp_value, 0, value);
@@ -1082,7 +1085,8 @@ static inline bool cortexar_mem_read_fast(target_s *const target, uint32_t *cons
10821085
for (size_t offset = 0; offset < count; ++offset) {
10831086
if (!cortexar_run_read_insn(target, ARM_LDC_R0_POSTINC4_DTRTX_INSN, dest + offset))
10841087
return false; /* Propagate failure if it happens */
1085-
if (target->target_options & TOPT_FLAVOUR_BE) {
1088+
extern bool skip_swap;
1089+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap) {
10861090
uint8_t value[4];
10871091
// The instruction run gave us back a value that we interpreted as little endian, however
10881092
write_le4(value, 0, dest[offset]);
@@ -1226,7 +1230,8 @@ static inline bool cortexar_mem_write_fast(target_s *const target, const uint32_
12261230
/* Write each of the uint32_t's checking for failure */
12271231
for (size_t offset = 0; offset < count; ++offset) {
12281232
uint32_t value;
1229-
if (target->target_options & TOPT_FLAVOUR_BE)
1233+
extern bool skip_swap;
1234+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap)
12301235
value = read_be4((const void *)src, offset * 4U);
12311236
else
12321237
value = read_le4((const void *)src, offset * 4U);
@@ -1330,25 +1335,26 @@ static void cortexar_regs_read(target_s *const target, void *const data)
13301335
{
13311336
const cortexar_priv_s *const priv = (cortexar_priv_s *)target->priv;
13321337
uint32_t *const regs = (uint32_t *)data;
1338+
extern bool skip_swap;
13331339
/* Copy the register values out from our cache */
13341340
for (size_t reg_index = 0; reg_index < sizeof(priv->core_regs.r) / sizeof(*priv->core_regs.r); reg_index++)
1335-
if (target->target_options & TOPT_FLAVOUR_BE)
1341+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap)
13361342
write_be4(data, reg_index * 4, priv->core_regs.r[reg_index]);
13371343
else
13381344
write_le4(data, reg_index * 4, priv->core_regs.r[reg_index]);
1339-
if (target->target_options & TOPT_FLAVOUR_BE) {
1345+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap) {
13401346
uint8_t value[4];
13411347
write_le4(value, 0, priv->core_regs.cpsr);
13421348
regs[CORTEX_REG_CPSR] = read_be4(value, 0);
13431349
} else
13441350
regs[CORTEX_REG_CPSR] = priv->core_regs.cpsr;
13451351
if (target->target_options & TOPT_FLAVOUR_FLOAT) {
13461352
for (size_t reg_index = 0; reg_index < sizeof(priv->core_regs.d) / sizeof(*priv->core_regs.d); reg_index++)
1347-
if (target->target_options & TOPT_FLAVOUR_BE)
1353+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap)
13481354
write_be4(data, (CORTEXAR_GENERAL_REG_COUNT + reg_index) * 4, priv->core_regs.d[reg_index]);
13491355
else
13501356
write_le4(data, (CORTEXAR_GENERAL_REG_COUNT + reg_index) * 4, priv->core_regs.d[reg_index]);
1351-
if (target->target_options & TOPT_FLAVOUR_BE) {
1357+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap) {
13521358
uint8_t value[4];
13531359
write_le4(value, 0, priv->core_regs.fpcsr);
13541360
regs[CORTEX_REG_FPCSR] = read_be4(value, 0);
@@ -1361,25 +1367,26 @@ static void cortexar_regs_write(target_s *const target, const void *const data)
13611367
{
13621368
cortexar_priv_s *const priv = (cortexar_priv_s *)target->priv;
13631369
const uint32_t *const regs = (const uint32_t *)data;
1370+
extern bool skip_swap;
13641371
/* Copy the new register values into our cache */
13651372
for (size_t reg_index = 0; reg_index < sizeof(priv->core_regs.r) / sizeof(*priv->core_regs.r); reg_index++)
1366-
if (target->target_options & TOPT_FLAVOUR_BE)
1373+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap)
13671374
priv->core_regs.r[reg_index] = read_be4(data, reg_index * 4);
13681375
else
13691376
priv->core_regs.r[reg_index] = read_le4(data, reg_index * 4);
1370-
if (target->target_options & TOPT_FLAVOUR_BE) {
1377+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap) {
13711378
uint8_t value[4];
13721379
write_le4(value, 0, regs[CORTEX_REG_CPSR]);
13731380
priv->core_regs.cpsr = read_be4(value, 0);
13741381
} else
13751382
priv->core_regs.cpsr = regs[CORTEX_REG_CPSR];
13761383
if (target->target_options & TOPT_FLAVOUR_FLOAT) {
13771384
for (size_t reg_index = 0; reg_index < sizeof(priv->core_regs.r) / sizeof(*priv->core_regs.r); reg_index++)
1378-
if (target->target_options & TOPT_FLAVOUR_BE)
1385+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap)
13791386
priv->core_regs.d[reg_index] = read_be4(data, (reg_index + CORTEXAR_GENERAL_REG_COUNT) * 4);
13801387
else
13811388
priv->core_regs.d[reg_index] = read_le4(data, (reg_index + CORTEXAR_GENERAL_REG_COUNT) * 4);
1382-
if (target->target_options & TOPT_FLAVOUR_BE) {
1389+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap) {
13831390
uint8_t value[4];
13841391
write_le4(value, 0, regs[CORTEX_REG_FPCSR]);
13851392
priv->core_regs.fpcsr = read_be4(value, 0);
@@ -1420,6 +1427,7 @@ static size_t cortexar_reg_width(const size_t reg)
14201427

14211428
static size_t cortexar_reg_read(target_s *const target, const uint32_t reg, void *const data, const size_t max)
14221429
{
1430+
extern bool skip_swap;
14231431
/* Try to get a pointer to the storage for the requested register, and return -1 if that fails */
14241432
const void *const reg_ptr = cortexar_reg_ptr(target, reg);
14251433
if (!reg_ptr)
@@ -1432,7 +1440,7 @@ static size_t cortexar_reg_read(target_s *const target, const uint32_t reg, void
14321440
switch (reg_width) {
14331441
case 4: {
14341442
uint32_t value;
1435-
if (target->target_options & TOPT_FLAVOUR_BE)
1443+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap)
14361444
value = read_be4(reg_ptr, 0);
14371445
else
14381446
value = read_le4(reg_ptr, 0);
@@ -1441,7 +1449,7 @@ static size_t cortexar_reg_read(target_s *const target, const uint32_t reg, void
14411449
}
14421450
case 8: {
14431451
uint64_t value;
1444-
if (target->target_options & TOPT_FLAVOUR_BE)
1452+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap)
14451453
value = read_be8(reg_ptr, 0);
14461454
else
14471455
value = read_le8(reg_ptr, 0);
@@ -1454,6 +1462,7 @@ static size_t cortexar_reg_read(target_s *const target, const uint32_t reg, void
14541462

14551463
static size_t cortexar_reg_write(target_s *const target, const uint32_t reg, const void *const data, const size_t max)
14561464
{
1465+
extern bool skip_swap;
14571466
/* Try to get a pointer to the storage for the requested register, and return -1 if that fails */
14581467
void *const reg_ptr = cortexar_reg_ptr(target, reg);
14591468
if (!reg_ptr)
@@ -1466,15 +1475,15 @@ static size_t cortexar_reg_write(target_s *const target, const uint32_t reg, con
14661475
switch (reg_width) {
14671476
case 4: {
14681477
uint32_t value = read_le4(data, 0);
1469-
if (target->target_options & TOPT_FLAVOUR_BE) {
1478+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap)
14701479
write_be4(reg_ptr, 0, value);
1471-
} else
1480+
else
14721481
write_le4(reg_ptr, 0, value);
14731482
break;
14741483
}
14751484
case 8: {
14761485
uint64_t value = read_le8(data, 0);
1477-
if (target->target_options & TOPT_FLAVOUR_BE)
1486+
if ((target->target_options & TOPT_FLAVOUR_BE) && !skip_swap)
14781487
write_be8(reg_ptr, 0, value);
14791488
else
14801489
write_le8(reg_ptr, 0, value);
@@ -1520,7 +1529,7 @@ static void cortexar_reset(target_s *const target)
15201529
#endif
15211530

15221531
/* 10ms delay to ensure bootroms have had time to run */
1523-
platform_delay(10);
1532+
// platform_delay(10);
15241533
/* Ignore any initial errors out of reset */
15251534
target_check_error(target);
15261535
}
@@ -1628,6 +1637,10 @@ static void cortexar_halt_resume(target_s *const target, const bool step)
16281637
/* Invalidate all the instruction caches if we're on a VMSA model device */
16291638
if (target->target_options & TOPT_FLAVOUR_VIRT_MEM)
16301639
cortexar_coproc_write(target, CORTEXAR_ICIALLU, 0U);
1640+
else {
1641+
cortexar_coproc_write(target, CORTEXAR_ICIALLU, 0U);
1642+
// cortexar_run_insn(target, ARM_ISB_INSN);
1643+
}
16311644
/* Mark the fault status and address cache invalid */
16321645
priv->core_status &= ~CORTEXAR_STATUS_FAULT_CACHE_VALID;
16331646

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