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cortexar: hack to get tms570 working
This gets basic debugging working, including breakpoints, single-stepping, memory access, and register access. Signed-off-by: Sean Cross <[email protected]>
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‎src/target/cortexar.c‎

Lines changed: 33 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,12 @@
5959

6060
#include <assert.h>
6161

62+
static uint32_t swap32(const uint32_t value)
63+
{
64+
return ((value >> 24) & 0xff) | ((value >> 8) & 0xff00) | ((value << 8) & 0xff0000) | ((value << 24) & 0xff000000);
65+
// return value;
66+
}
67+
6268
typedef struct cortexar_priv {
6369
/* Base core information */
6470
cortex_priv_s base;
@@ -286,10 +292,10 @@ static const uint16_t cortexar_spsr_encodings[5] = {
286292
* The fourth is `STRH r1, [r0], #+2` to store a uint16_t to [r0] from r1 and increment
287293
* the address in r0 by 2, writing the new address back to r0.
288294
*/
289-
#define ARM_LDRB_R0_R1_INSN 0xe4f01001U
290-
#define ARM_LDRH_R0_R1_INSN 0xe0f010b2U
291-
#define ARM_STRB_R1_R0_INSN 0xe4e01001U
292-
#define ARM_STRH_R1_R0_INSN 0xe0e010b2U
295+
#define ARM_LDRB_R0_R1_INSN 0xe4d01001U
296+
#define ARM_LDRH_R0_R1_INSN 0xe0d010b2U
297+
#define ARM_STRB_R1_R0_INSN 0xe4c01001U
298+
#define ARM_STRH_R1_R0_INSN 0xe0c010b2U
293299

294300
/* Instruction encodings for synchronisation barriers */
295301
#define ARM_ISB_INSN 0xe57ff06fU
@@ -1021,7 +1027,7 @@ static inline bool cortexar_mem_read_fast(target_s *const target, uint32_t *cons
10211027
/* Run the transfer, hammering the DTR */
10221028
for (size_t offset = 0; offset < count; ++offset) {
10231029
/* Read the next value, which is the value for the last instruction run */
1024-
const uint32_t value = adiv5_dp_read(priv->base.ap->dp, ADIV5_AP_DB(CORTEXAR_BANKED_DTRRX));
1030+
const uint32_t value = swap32(adiv5_dp_read(priv->base.ap->dp, ADIV5_AP_DB(CORTEXAR_BANKED_DTRRX)));
10251031
/* If we've run the instruction at least once, store it */
10261032
if (offset)
10271033
dest[offset - 1U] = value;
@@ -1031,7 +1037,7 @@ static inline bool cortexar_mem_read_fast(target_s *const target, uint32_t *cons
10311037
/* Go back into DCC Normal (Non-blocking) mode */
10321038
adiv5_dp_write(priv->base.ap->dp, ADIV5_AP_DB(CORTEXAR_BANKED_DCSR), dbg_dcsr | CORTEXAR_DBG_DCSR_DCC_NORMAL);
10331039
/* Grab the value of the last instruction run now it won't run again */
1034-
dest[count - 1U] = adiv5_dp_read(priv->base.ap->dp, ADIV5_AP_DB(CORTEXAR_BANKED_DTRRX));
1040+
dest[count - 1U] = swap32(adiv5_dp_read(priv->base.ap->dp, ADIV5_AP_DB(CORTEXAR_BANKED_DTRRX)));
10351041
/* Check if the instruction triggered a synchronous data abort */
10361042
return cortexar_check_data_abort(target, status);
10371043
}
@@ -1040,6 +1046,7 @@ static inline bool cortexar_mem_read_fast(target_s *const target, uint32_t *cons
10401046
for (size_t offset = 0; offset < count; ++offset) {
10411047
if (!cortexar_run_read_insn(target, ARM_LDC_R0_POSTINC4_DTRTX_INSN, dest + offset))
10421048
return false; /* Propagate failure if it happens */
1049+
dest[offset] = swap32(dest[offset]);
10431050
}
10441051
return true; /* Signal success */
10451052
}
@@ -1165,7 +1172,7 @@ static inline bool cortexar_mem_write_fast(target_s *const target, const uint32_
11651172
adiv5_dp_write(priv->base.ap->dp, ADIV5_AP_DB(CORTEXAR_BANKED_ITR), ARM_STC_DTRRX_R0_POSTINC4_INSN);
11661173
/* Run the transfer, hammering the DTR */
11671174
for (size_t offset = 0; offset < count; ++offset)
1168-
adiv5_dp_write(priv->base.ap->dp, ADIV5_AP_DB(CORTEXAR_BANKED_DTRTX), src[offset]);
1175+
adiv5_dp_write(priv->base.ap->dp, ADIV5_AP_DB(CORTEXAR_BANKED_DTRTX), swap32(src[offset]));
11691176
/* Now read out the status from the DCSR in case anything went wrong */
11701177
const uint32_t status = adiv5_dp_read(priv->base.ap->dp, ADIV5_AP_DB(CORTEXAR_BANKED_DCSR));
11711178
/* Go back into DCC Normal (Non-blocking) mode */
@@ -1176,7 +1183,7 @@ static inline bool cortexar_mem_write_fast(target_s *const target, const uint32_
11761183

11771184
/* Write each of the uint32_t's checking for failure */
11781185
for (size_t offset = 0; offset < count; ++offset) {
1179-
if (!cortexar_run_write_insn(target, ARM_STC_DTRRX_R0_POSTINC4_INSN, src[offset]))
1186+
if (!cortexar_run_write_insn(target, ARM_STC_DTRRX_R0_POSTINC4_INSN, swap32(src[offset])))
11801187
return false; /* Propagate failure if it happens */
11811188
}
11821189
return true; /* Signal success */
@@ -1272,16 +1279,24 @@ static void cortexar_mem_write(
12721279
cortexar_halt_resume(target, false);
12731280
}
12741281

1282+
static void memcpy_swap(void *dest_v, const void *src_v, size_t count) {
1283+
uint8_t *dest = dest_v;
1284+
const uint8_t *src = src_v;
1285+
for (size_t i = 0; i < count; i += 1) {
1286+
dest[(i&~3)+(~i&3)] = src[i];
1287+
}
1288+
}
1289+
12751290
static void cortexar_regs_read(target_s *const target, void *const data)
12761291
{
12771292
const cortexar_priv_s *const priv = (cortexar_priv_s *)target->priv;
12781293
uint32_t *const regs = (uint32_t *)data;
12791294
/* Copy the register values out from our cache */
1280-
memcpy(regs, priv->core_regs.r, sizeof(priv->core_regs.r));
1281-
regs[CORTEX_REG_CPSR] = priv->core_regs.cpsr;
1295+
memcpy_swap(regs, priv->core_regs.r, sizeof(priv->core_regs.r));
1296+
regs[CORTEX_REG_CPSR] = swap32(priv->core_regs.cpsr);
12821297
if (target->target_options & TOPT_FLAVOUR_FLOAT) {
1283-
memcpy(regs + CORTEXAR_GENERAL_REG_COUNT, priv->core_regs.d, sizeof(priv->core_regs.d));
1284-
regs[CORTEX_REG_FPCSR] = priv->core_regs.fpcsr;
1298+
memcpy_swap(regs + CORTEXAR_GENERAL_REG_COUNT, priv->core_regs.d, sizeof(priv->core_regs.d));
1299+
regs[CORTEX_REG_FPCSR] = swap32(priv->core_regs.fpcsr);
12851300
}
12861301
}
12871302

@@ -1290,11 +1305,11 @@ static void cortexar_regs_write(target_s *const target, const void *const data)
12901305
cortexar_priv_s *const priv = (cortexar_priv_s *)target->priv;
12911306
const uint32_t *const regs = (const uint32_t *)data;
12921307
/* Copy the new register values into our cache */
1293-
memcpy(priv->core_regs.r, regs, sizeof(priv->core_regs.r));
1294-
priv->core_regs.cpsr = regs[CORTEX_REG_CPSR];
1308+
memcpy_swap(priv->core_regs.r, regs, sizeof(priv->core_regs.r));
1309+
priv->core_regs.cpsr = swap32(regs[CORTEX_REG_CPSR]);
12951310
if (target->target_options & TOPT_FLAVOUR_FLOAT) {
1296-
memcpy(priv->core_regs.d, regs + CORTEXAR_GENERAL_REG_COUNT, sizeof(priv->core_regs.d));
1297-
priv->core_regs.fpcsr = regs[CORTEX_REG_FPCSR];
1311+
memcpy_swap(priv->core_regs.d, regs + CORTEXAR_GENERAL_REG_COUNT, sizeof(priv->core_regs.d));
1312+
priv->core_regs.fpcsr = swap32(regs[CORTEX_REG_FPCSR]);
12981313
}
12991314
}
13001315

@@ -1339,7 +1354,7 @@ static size_t cortexar_reg_read(target_s *const target, const uint32_t reg, void
13391354
if (max < reg_width)
13401355
return 0;
13411356
/* Finally, copy the register data out and return the width */
1342-
memcpy(data, reg_ptr, reg_width);
1357+
memcpy_swap(data, reg_ptr, reg_width);
13431358
return reg_width;
13441359
}
13451360

@@ -1354,7 +1369,7 @@ static size_t cortexar_reg_write(target_s *const target, const uint32_t reg, con
13541369
if (max < reg_width)
13551370
return 0;
13561371
/* Finally, copy the new register data in and return the width */
1357-
memcpy(reg_ptr, data, reg_width);
1372+
memcpy_swap(reg_ptr, data, reg_width);
13581373
return reg_width;
13591374
}
13601375

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