@@ -84,18 +84,6 @@ static bool nrf91_wait_ready(target_s *const target, platform_timeout_s *const t
8484 return true;
8585}
8686
87- static bool nrf91_wait_readynext (target_s * const target , platform_timeout_s * const timeout )
88- {
89- /* Poll for NVMC_READY */
90- while (target_mem_read32 (target , NRF91_NVMC_READYNEXT ) == 0 ) {
91- if (target_check_error (target ))
92- return false;
93- if (timeout )
94- target_print_progress (timeout );
95- }
96- return true;
97- }
98-
9987static bool nrf91_flash_erase (target_flash_s * flash , target_addr_t addr , size_t len )
10088{
10189 target_s * target = flash -> t ;
@@ -140,20 +128,14 @@ static bool nrf91_uicr_flash_erase(target_flash_s *flash, target_addr_t addr, si
140128static bool nrf91_flash_write (target_flash_s * flash , target_addr_t dest , const void * src , size_t len )
141129{
142130 target_s * target = flash -> t ;
143- platform_timeout_s timeout ;
131+
144132 /* Enable write */
145133 target_mem_write32 (target , NRF91_NVMC_CONFIG , NRF91_NVMC_CONFIG_WEN );
146-
147- if (!nrf91_wait_ready (target , & timeout ))
134+ if (!nrf91_wait_ready (target , NULL ))
148135 return false;
149136 /* Write the data */
150- for (size_t offset = 0 ; offset < len ; offset += 4 ) {
151- target_mem_write32 (target , dest + offset , src + offset );
152- if (!nrf91_wait_readynext (target , & timeout ))
153- return false;
154- }
155- //target_mem_write(target, dest, src, len);
156- if (!nrf91_wait_ready (target , & timeout ))
137+ target_mem_write (target , dest , src , len );
138+ if (!nrf91_wait_ready (target , NULL ))
157139 return false;
158140 /* Return to read-only */
159141 target_mem_write32 (target , NRF91_NVMC_CONFIG , NRF91_NVMC_CONFIG_REN );
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