3232#include "timing.h"
3333#include "timing_stm32.h"
3434
35- #define PLATFORM_HAS_TRACESWO
36- #define NUM_TRACE_PACKETS 256U /* 16K buffer */
37- #define TRACESWO_PROTOCOL 2U /* 1 = RZ/Manchester, 2 = NRZ/async/uart */
38-
3935#if ENABLE_DEBUG == 1
4036#define PLATFORM_HAS_DEBUG
4137extern bool debug_bmp ;
@@ -285,10 +281,22 @@ extern bool debug_bmp;
285281#define IRQ_PRI_TRACE (0U << 4U)
286282#define IRQ_PRI_SWO_DMA (0U << 4U)
287283
288- #define TRACE_TIM TIM3
289- #define TRACE_TIM_CLK_EN () rcc_periph_clock_enable(RCC_TIM3)
290- #define TRACE_IRQ NVIC_TIM3_IRQ
291- #define TRACE_ISR (x ) tim3_isr(x)
284+ #define PLATFORM_HAS_TRACESWO
285+ #define NUM_TRACE_PACKETS 256U /* 16K buffer */
286+ //#define TRACESWO_PROTOCOL 2U /* 1 = RZ/Manchester, 2 = NRZ/async/uart */
287+
288+ #if TRACESWO_PROTOCOL == 1
289+
290+ /* Use TIM4 Input 2 (from PB7/TDO) or Input 1 (from PB6/TDO), AF2, trigger on Rising Edge */
291+ #define TRACE_TIM TIM4
292+ #define TRACE_TIM_CLK_EN () rcc_periph_clock_enable(RCC_TIM4)
293+ #define TRACE_IRQ NVIC_TIM4_IRQ
294+ #define TRACE_ISR (x ) tim4_isr(x)
295+ #define TRACE_IC_IN PINOUT_SWITCH(TIM_IC_IN_TI2, TIM_IC_IN_TI1)
296+ #define TRACE_TRIG_IN TIM_SMCR_TS_TI1FP1
297+ #define TRACE_TIM_PIN_AF GPIO_AF2
298+
299+ #elif TRACESWO_PROTOCOL == 2
292300
293301/* On F411 use USART1_RX mapped on PB7 for async capture */
294302#define SWO_UART USBUSART1
@@ -299,12 +307,14 @@ extern bool debug_bmp;
299307#define SWO_UART_PIN_AF GPIO_AF7
300308
301309/* Bind to the same DMA Rx channel */
302- #define SWO_DMA_BUS USBUSART1_DMA_BUS
303- #define SWO_DMA_CLK USBUSART1_DMA_CLK
304- #define SWO_DMA_CHAN USBUSART1_DMA_RX_CHAN
305- #define SWO_DMA_IRQ USBUSART1_DMA_RX_IRQ
306- #define SWO_DMA_ISR (x ) USBUSART1_DMA_RX_ISRx(x)
307- #define SWO_DMA_TRG DMA_SxCR_CHSEL_4
310+ #define SWO_DMA_BUS USBUSART1_DMA_BUS
311+ #define SWO_DMA_CLK USBUSART1_DMA_CLK
312+ #define SWO_DMA_CHAN USBUSART1_DMA_RX_CHAN
313+ #define SWO_DMA_IRQ USBUSART1_DMA_RX_IRQ
314+ #define SWO_DMA_ISR (x ) USBUSART1_DMA_RX_ISRx(x)
315+ #define SWO_DMA_TRG DMA_SxCR_CHSEL_4
316+
317+ #endif /* TRACESWO_PROTOCOL */
308318
309319#define SET_RUN_STATE (state ) \
310320 { \
0 commit comments