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common/stm32/timing: Treat _no_delay frequency specially
* Current _clk_delay strategy is better approximated by a proportional law, but _no_delay does not fit into that nicely. * Also update delay macros with values obtained from calibration.
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src/platforms/common/stm32/timing_stm32.c

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -146,9 +146,26 @@ uint32_t platform_time_ms(void)
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* per delay loop count with 2 delay loops per clock
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*/
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149+
#if defined(STM32F4)
150+
/* Values for STM32F411 at 96 MHz */
151+
#define USED_SWD_CYCLES_NODELAY 12
152+
#define USED_SWD_CYCLES 24
153+
#define CYCLES_PER_CNT 12
154+
#elif defined(STM32F1)
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/* Values for STM32F103 at 72 MHz */
156+
#define USED_SWD_CYCLES_NODELAY 14
157+
#define USED_SWD_CYCLES 30
158+
#define CYCLES_PER_CNT 14
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#elif defined(STM32F0)
160+
/* Values for STM32F072 at 48 MHz */
161+
#define USED_SWD_CYCLES_NODELAY 24
162+
#define USED_SWD_CYCLES 30
163+
#define CYCLES_PER_CNT 17
164+
#else
165+
/* Inherit defaults for other platforms (F3, F7) */
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#define USED_SWD_CYCLES 22
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#define CYCLES_PER_CNT 10
168+
#endif
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void platform_max_frequency_set(const uint32_t frequency)
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{
@@ -200,8 +217,10 @@ uint32_t platform_max_frequency_get(void)
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const uint32_t ratio = (target_clk_divider * BITBANG_DIVIDER_FACTOR) + BITBANG_DIVIDER_OFFSET;
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return rcc_ahb_frequency / ratio;
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#else
220+
if (target_clk_divider == UINT32_MAX)
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return rcc_ahb_frequency / USED_SWD_CYCLES_NODELAY;
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uint32_t result = rcc_ahb_frequency;
204-
result /= USED_SWD_CYCLES + CYCLES_PER_CNT * target_clk_divider;
223+
result /= USED_SWD_CYCLES + CYCLES_PER_CNT * target_clk_divider * 2U;
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return result;
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#endif
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}

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