Skip to content

Commit 3177cd1

Browse files
xobsxobs
committed
fixup clang-formatting
Signed-off-by: Sean Cross <[email protected]>
1 parent 0a7e240 commit 3177cd1

File tree

2 files changed

+79
-43
lines changed

2 files changed

+79
-43
lines changed

‎src/target/cortexar.c‎

Lines changed: 44 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -250,7 +250,7 @@ static const uint16_t cortexar_spsr_encodings[5] = {
250250
(((opc1) << 21U) | ((crn) << 16U) | ((rt) << 12U) | ((coproc) << 8U) | ((opc2) << 5U) | (crm))
251251
/* Packs a CRn and CRm value for the coprocessor IO routines below to unpack */
252252
#define ENCODE_CP_REG(n, m, opc1, opc2) \
253-
((((n)&0xfU) << 4U) | ((m)&0xfU) | (((opc1)&0x7U) << 8U) | (((opc2)&0x7U) << 12U))
253+
((((n) & 0xfU) << 4U) | ((m) & 0xfU) | (((opc1) & 0x7U) << 8U) | (((opc2) & 0x7U) << 12U))
254254

255255
/*
256256
* Instruction encodings for coprocessor load/store
@@ -935,10 +935,10 @@ bool cortexr_probe(adiv5_access_port_s *const ap, const target_addr_t base_addre
935935
return false;
936936

937937
switch (target->designer_code) {
938-
/* TI omitted the designer code on TMS570 */
939-
case 0:
940-
PROBE(ti_tms570_probe);
941-
break;
938+
/* TI omitted the designer code on TMS570 */
939+
case 0:
940+
PROBE(ti_tms570_probe);
941+
break;
942942
}
943943

944944
#if CONFIG_BMDA == 0
@@ -1014,12 +1014,12 @@ static bool cortexar_check_error(target_s *const target)
10141014
{
10151015
cortexar_priv_s *const priv = (cortexar_priv_s *)target->priv;
10161016
const bool fault = priv->core_status & (CORTEXAR_STATUS_DATA_FAULT | CORTEXAR_STATUS_MMU_FAULT);
1017-
priv->core_status &= (uint8_t) ~(CORTEXAR_STATUS_DATA_FAULT | CORTEXAR_STATUS_MMU_FAULT);
1017+
priv->core_status &= (uint8_t)~(CORTEXAR_STATUS_DATA_FAULT | CORTEXAR_STATUS_MMU_FAULT);
10181018
return fault || cortex_check_error(target);
10191019
}
10201020

1021-
1022-
static inline uint32_t cortexar_endian_dp_read(target_s *const target, const uint16_t addr) {
1021+
static inline uint32_t cortexar_endian_dp_read(target_s *const target, const uint16_t addr)
1022+
{
10231023
cortexar_priv_s *const priv = (cortexar_priv_s *)target->priv;
10241024
uint32_t value = adiv5_dp_read(priv->base.ap->dp, addr);
10251025
if (target->target_options & TOPT_FLAVOUR_BE) {
@@ -1032,7 +1032,8 @@ static inline uint32_t cortexar_endian_dp_read(target_s *const target, const uin
10321032
return value;
10331033
}
10341034

1035-
static inline void cortexar_endian_dp_write(target_s *const target, const uint16_t addr, uint32_t value) {
1035+
static inline void cortexar_endian_dp_write(target_s *const target, const uint16_t addr, uint32_t value)
1036+
{
10361037
cortexar_priv_s *const priv = (cortexar_priv_s *)target->priv;
10371038

10381039
if (target->target_options & TOPT_FLAVOUR_BE) {
@@ -1429,24 +1430,24 @@ static size_t cortexar_reg_read(target_s *const target, const uint32_t reg, void
14291430
return 0;
14301431
/* Finally, copy the register data out and return the width */
14311432
switch (reg_width) {
1432-
case 4: {
1433-
uint32_t value;
1434-
if (target->target_options & TOPT_FLAVOUR_BE)
1435-
value = read_be4(reg_ptr, 0);
1436-
else
1437-
value = read_le4(reg_ptr, 0);
1438-
write_le4(data, 0, value);
1439-
break;
1440-
}
1441-
case 8: {
1442-
uint64_t value;
1443-
if (target->target_options & TOPT_FLAVOUR_BE)
1444-
value = read_be8(reg_ptr, 0);
1445-
else
1446-
value = read_le8(reg_ptr, 0);
1447-
write_le8(data, 0, value);
1448-
break;
1449-
}
1433+
case 4: {
1434+
uint32_t value;
1435+
if (target->target_options & TOPT_FLAVOUR_BE)
1436+
value = read_be4(reg_ptr, 0);
1437+
else
1438+
value = read_le4(reg_ptr, 0);
1439+
write_le4(data, 0, value);
1440+
break;
1441+
}
1442+
case 8: {
1443+
uint64_t value;
1444+
if (target->target_options & TOPT_FLAVOUR_BE)
1445+
value = read_be8(reg_ptr, 0);
1446+
else
1447+
value = read_le8(reg_ptr, 0);
1448+
write_le8(data, 0, value);
1449+
break;
1450+
}
14501451
}
14511452
return reg_width;
14521453
}
@@ -1463,22 +1464,22 @@ static size_t cortexar_reg_write(target_s *const target, const uint32_t reg, con
14631464
return 0;
14641465
/* Finally, copy the new register data in and return the width */
14651466
switch (reg_width) {
1466-
case 4: {
1467-
uint32_t value = read_le4(data, 0);
1468-
if (target->target_options & TOPT_FLAVOUR_BE) {
1469-
write_be4(reg_ptr, 0, value);
1470-
} else
1471-
write_le4(reg_ptr, 0, value);
1472-
break;
1473-
}
1474-
case 8: {
1475-
uint64_t value = read_le8(data, 0);
1476-
if (target->target_options & TOPT_FLAVOUR_BE)
1477-
write_be8(reg_ptr, 0, value);
1478-
else
1479-
write_le8(reg_ptr, 0, value);
1480-
break;
1481-
}
1467+
case 4: {
1468+
uint32_t value = read_le4(data, 0);
1469+
if (target->target_options & TOPT_FLAVOUR_BE) {
1470+
write_be4(reg_ptr, 0, value);
1471+
} else
1472+
write_le4(reg_ptr, 0, value);
1473+
break;
1474+
}
1475+
case 8: {
1476+
uint64_t value = read_le8(data, 0);
1477+
if (target->target_options & TOPT_FLAVOUR_BE)
1478+
write_be8(reg_ptr, 0, value);
1479+
else
1480+
write_le8(reg_ptr, 0, value);
1481+
break;
1482+
}
14821483
}
14831484
return reg_width;
14841485
}

‎src/target/ti_tms570.c‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,29 @@
88
#define TMS570_SCM_DEVID_ID_MASK 0x0700fe7fU /* Note: value is swapped since target is BE */
99
#define TMS570_SCM_REVID_ID_TMS570 0x05004400U /* Note: value is swapped since target is BE */
1010

11+
#define TMS570_OTP_BANK0_MEMORY_INFORMATION 0xF008015CU
12+
#define TMS570_OTP_BANK0_MEMORY_SIZE_MASK 0xFFFFU
13+
1114
/* Base address for the OCRAM regions, including their mirrors (including RETRAM) */
1215
#define TMS570_SRAM_BASE 0x08000000U
1316
#define TMS570_SRAM_ECC_BASE 0x08400000U
1417
#define TMS570_SRAM_SIZE 0x80000U
1518

19+
#define TMS570_FLASH_BASE_ADDR 0x00000000U
20+
#define TMS570_FLASH_SECTOR_ADDR 0xFFF87408U
21+
#define TMS570_FLASH_SECTOR_SIZE
22+
1623
#define TMS570_OTP_PACKAGE_AND_FLASH_MEMORY_SIZE 0xf008015cU
1724

25+
/*
26+
* Flash functions
27+
*/
28+
static bool tms570_flash_erase(target_flash_s *flash, target_addr_t addr, size_t len);
29+
static bool tms570_flash_write(target_flash_s *flash, target_addr_t dest, const void *src, size_t len);
30+
static bool tms570_flash_prepare(target_flash_s *flash);
31+
static bool tms570_flash_done(target_flash_s *flash);
32+
33+
1834
bool ti_tms570_probe(target_s *const target)
1935
{
2036
const uint32_t part_id = target_mem32_read32(target, TMS570_SYS_DEVID);
@@ -27,5 +43,24 @@ bool ti_tms570_probe(target_s *const target)
2743
target_add_ram32(target, TMS570_SRAM_BASE, TMS570_SRAM_SIZE);
2844
target_add_ram32(target, TMS570_SRAM_ECC_BASE, TMS570_SRAM_SIZE);
2945

46+
// const uint32_t flash_size = (target_mem32_read32(target, TMS570_OTP_BANK0_MEMORY_INFORMATION) & TMS570_OTP_BANK0_MEMORY_SIZE_MASK) * 1024;
47+
48+
// target_flash_s *flash = calloc(1, sizeof(*flash));
49+
// if (!flash) { /* calloc failed: heap exhaustion */
50+
// DEBUG_ERROR("calloc: failed in %s\n", __func__);
51+
// return false;
52+
// }
53+
54+
// flash->start = TMS570_FLASH_BASE_ADDR;
55+
// flash->length = flash_size;
56+
// flash->blocksize = TMS570_FLASH_SECTOR_SIZE;
57+
// flash->writesize = CH579_FLASH_WRITE_SIZE;
58+
// flash->erase = tms570_flash_erase;
59+
// flash->write = tms570_flash_write;
60+
// flash->prepare = tms570_flash_prepare;
61+
// flash->done = tms570_flash_done;
62+
// flash->erased = 0xffU;
63+
// target_add_flash(target, flash);
64+
3065
return true;
3166
}

0 commit comments

Comments
 (0)