Week 3 Updated

Author: mdrohansheikh

.github/workflows/c-cpp.yml

@@ -0,0 +1,23 @@
+name: C/C++ CI
+
+on:
+  push:
+    branches: [ "main" ]
+  pull_request:
+    branches: [ "main" ]
+
+jobs:
+  build:
+
+    runs-on: ubuntu-latest
+
+    steps:
+    - uses: actions/checkout@v4
+    - name: configure
+      run: ./configure
+    - name: make
+      run: make
+    - name: make check
+      run: make check
+    - name: make distcheck
+      run: make distcheck

.vscode/tasks.json

@@ -2,14 +2,23 @@
     "tasks": [
         {
             "type": "cppbuild",
+<<<<<<< HEAD
             "label": "C/C++: g++ build active file",
             "command": "/usr/bin/g++",
+=======
+            "label": "C/C++: g++.exe build active file",
+            "command": "C:\\msys64\\ucrt64\\bin\\g++.exe",
+>>>>>>> c70d70303a5d72c4a39d48491cf8e55b7bd81225
             "args": [
                 "-fdiagnostics-color=always",
                 "-g",
                 "${file}",
                 "-o",
+<<<<<<< HEAD
                 "${fileDirname}/${fileBasenameNoExtension}"
+=======
+                "${fileDirname}\\${fileBasenameNoExtension}.exe"
+>>>>>>> c70d70303a5d72c4a39d48491cf8e55b7bd81225
             ],
             "options": {
                 "cwd": "${fileDirname}"

README.md

@@ -118,4 +118,8 @@ Coming Soon.
 ## License 🛠️
 Open License. Feel Free to use & Modify
 
-**Primary Contact:** 📬 MD. Rohan, Mail: [email protected] 
+<<<<<<< HEAD
+**Primary Contact:** 📬 MD. Rohan, Mail: [email protected] 
+=======
+**Primary Contact:** 📬 MD. Rohan, Mail: [email protected] 
+>>>>>>> c70d70303a5d72c4a39d48491cf8e55b7bd81225

Week 1/Week1.md

@@ -87,4 +87,8 @@
 - **Boost**: For a wide range of utility libraries.
 - **Google Test**: For unit testing.
 - **CMake**: For build automation.
-- **GitHub/GitLab**: For version control.
+<<<<<<< HEAD
+- **GitHub/GitLab**: For version control.
+=======
+- **GitHub/GitLab**: For version control.
+>>>>>>> c70d70303a5d72c4a39d48491cf8e55b7bd81225

Week 2/Assembler.cpp

@@ -48,4 +48,8 @@ int main() {
     cout << "\nMachine Code:\n" << assemble(assemblyCode) << endl;
 
     return 0;
-}
+<<<<<<< HEAD
+}
+=======
+}
+>>>>>>> c70d70303a5d72c4a39d48491cf8e55b7bd81225

Week 2/Assembler.exe

@@ -1,3 +1,4 @@
+<<<<<<< HEAD
 
 # Week 2: C++ Program for Assembling and Converting Assembly Code to Machine Code
 
@@ -127,4 +128,148 @@ END
 Machine Code:
 <converted machine code>
 ```
-- **Explanation**: The program first shows a sample input and its corresponding machine code output. It then prompts the user to enter their assembly code and converts it to machine code, displaying the result.
+- **Explanation**: The program first shows a sample input and its corresponding machine code output. It then prompts the user to enter their assembly code and converts it to machine code, displaying the result.
+=======
+# Week 2: Instruction Set Architecture (ISA)
+
+## Assembler Program Description
+
+The Assembler Program is a tool designed to convert assembly code into machine code. It allows users to write assembly instructions, which are then translated into the binary code that a CPU can execute. This program provides an intuitive interface for entering assembly instructions and viewing the corresponding machine code.
+
+### How to Use the Program
+
+1. **Input Assembly Code**:
+   - Enter your assembly instructions in the "Input" section. Each instruction should be on a new line.
+
+2. **Assemble the Code**:
+   - Click the "Assemble" button to convert the assembly code into machine code.
+
+3. **View Output**:
+   - The resulting machine code will be displayed in the "Output" section.
+
+### Sample Input and Output
+
+**Sample Input**:
+```assembly
+ADD R1, R2, R3
+SUB R4, R5, R6
+LOAD R1, [R2]
+STORE R3, [R4]
+```
+**Sample Output**:
+```text
+0001000100100011
+0010010001010110
+0011000100100000
+0100001101000000
+```
+
+### ADD:
+**Operation**: Adds the values from two registers and stores the result in a destination register.  
+**Format**: `ADD R1, R2, R3`  
+**Description**: `R1 = R2 + R3`
+
+### SUB:
+**Operation**: Subtracts the value of the second register from the first register and stores the result in the destination register.  
+**Format**: `SUB R1, R2, R3`  
+**Description**: `R1 = R2 - R3`
+
+### LOAD:
+**Operation**: Loads a value from memory into a register.  
+**Format**: `LOAD R1, [R2]`  
+**Description**: `R1 = Memory[R2]`
+
+### STORE:
+**Operation**: Stores the value from a register into memory.  
+**Format**: `STORE R1, [R2]`  
+**Description**: `Memory[R2] = R1`
+
+### MUL (Multiplication):
+**Operation**: Multiplies the values from two registers and stores the result in a destination register.  
+**Format**: `MUL R1, R2, R3`  
+**Description**: `R1 = R2 * R3`
+
+### DIV (Division):
+**Operation**: Divides the value of the first register by the value of the second register and stores the result in a destination register.  
+**Format**: `DIV R1, R2, R3`  
+**Description**: `R1 = R2 / R3`
+
+### AND (Bitwise AND):
+**Operation**: Performs a bitwise AND operation on two registers and stores the result in a destination register.  
+**Format**: `AND R1, R2, R3`  
+**Description**: `R1 = R2 & R3`
+
+### OR (Bitwise OR):
+**Operation**: Performs a bitwise OR operation on two registers and stores the result in a destination register.  
+**Format**: `OR R1, R2, R3`  
+**Description**: `R1 = R2 | R3`
+
+### XOR (Bitwise XOR):
+**Operation**: Performs a bitwise XOR operation on two registers and stores the result in a destination register.  
+**Format**: `XOR R1, R2, R3`  
+**Description**: `R1 = R2 ^ R3`
+
+### NOT (Bitwise NOT):
+**Operation**: Performs a bitwise NOT operation on a single register and stores the result in the same register.  
+**Format**: `NOT R1`  
+**Description**: `R1 = ~R1`
+
+### JMP (Jump):
+**Operation**: Jumps to a specified memory address.  
+**Format**: `JMP [address]`  
+**Description**: `PC = address`
+
+### JZ (Jump if Zero):
+**Operation**: Jumps to a specified memory address if the zero flag is set.  
+**Format**: `JZ [address]`  
+**Description**: `if (ZF == 1) PC = address`
+
+### JNZ (Jump if Not Zero):
+**Operation**: Jumps to a specified memory address if the zero flag is not set.  
+**Format**: `JNZ [address]`  
+**Description**: `if (ZF == 0) PC = address`
+
+### CALL (Call Subroutine):
+**Operation**: Calls a subroutine at a specified memory address.  
+**Format**: `CALL [address]`  
+**Description**: `SP = PC; PC = address`
+
+### RET (Return from Subroutine):
+**Operation**: Returns from a subroutine to the instruction following the CALL.  
+**Format**: `RET`  
+**Description**: `PC = SP`
+
+### CMP (Compare):
+**Operation**: Compares the values of two registers and sets the appropriate flags.  
+**Format**: `CMP R1, R2`  
+**Description**: `ZF = (R1 == R2); SF = (R1 < R2)`
+
+
+## Document the Instruction Formats:
+Each instruction can have a specific format, often including the opcode and operands. Here’s a simple example:
+
+| Instruction | Opcode | Format           | Description                      |
+|-------------|--------|------------------|----------------------------------|
+| ADD         | 0001   | ADD R1, R2, R3   | R1 = R2 + R3                     |
+| SUB         | 0010   | SUB R1, R2, R3   | R1 = R2 - R3                     |
+| LOAD        | 0011   | LOAD R1, [R2]    | R1 = Memory[R2]                  |
+| STORE       | 0100   | STORE R1, [R2]   | Memory[R2] = R1                  |
+| MUL         | 0101   | MUL R1, R2, R3   | R1 = R2 * R3                     |
+| DIV         | 0110   | DIV R1, R2, R3   | R1 = R2 / R3                     |
+| AND         | 0111   | AND R1, R2, R3   | R1 = R2 & R3                     |
+| OR          | 1000   | OR R1, R2, R3    | R1 = R2 | R3                     |
+| XOR         | 1001   | XOR R1, R2, R3   | R1 = R2 ^ R3                     |
+| NOT         | 1010   | NOT R1           | R1 = ~R1                         |
+| JMP         | 1011   | JMP [address]    | PC = address                     |
+| JZ          | 1100   | JZ [address]     | if (ZF == 1) PC = address        |
+| JNZ         | 1101   | JNZ [address]    | if (ZF == 0) PC = address        |
+| CALL        | 1110   | CALL [address]   | SP = PC; PC = address            |
+| RET         | 1111   | RET              | PC = SP                          |
+| CMP         | 0000   | CMP R1, R2       | ZF = (R1 == R2); SF = (R1 < R2)  |
+
+
+#### Create a Simple Assembler:
+1. **Parser**: Read assembly code and parse each line to identify the instruction and operands.
+2. **Opcode Mapping**: Create a mapping from instruction names to their corresponding opcode values.
+3. **Code Generation**: Convert parsed instructions into machine code by replacing instruction names with opcodes and resolving operand addresses.
+>>>>>>> c70d70303a5d72c4a39d48491cf8e55b7bd81225

Week 2/Week2.md

@@ -1,4 +1,5 @@
 #include <iostream>
+<<<<<<< HEAD
 #include <sstream>
 #include <map>
 #include <vector>
@@ -139,5 +140,66 @@ int main() {
     cout << "Final Register States:\n";
     cpu.registers.display();
 
+=======
+#include <vector>
+
+class ALU {
+public:
+    int performOperation(const std::string& operation, int operand1, int operand2) {
+        if (operation == "ADD") return operand1 + operand2;
+        if (operation == "SUB") return operand1 - operand2;
+        if (operation == "AND") return operand1 & operand2;
+        if (operation == "OR") return operand1 | operand2;
+        return 0; // Default case
+    }
+};
+
+class CPU {
+    int programCounter;
+    int instructionRegister;
+public:
+    CPU() : programCounter(0), instructionRegister(0) {}
+
+    int getPC() const { return programCounter; }
+    void setPC(int value) { programCounter = value; }
+
+    int getIR() const { return instructionRegister; }
+    void setIR(int value) { instructionRegister = value; }
+
+    void fetchInstruction(const std::vector<int>& memory) {
+        instructionRegister = memory[programCounter];
+        programCounter++;
+    }
+};
+
+class Registers {
+    int reg[4]; // Let's assume 4 general-purpose registers
+public:
+    int getRegister(int index) const { return reg[index]; }
+    void setRegister(int index, int value) { reg[index] = value; }
+};
+
+
+int main() {
+    ALU alu;
+    Registers regs;
+    CPU cpu;
+
+    std::vector<int> memory = {0x010203, 0x040506}; // Example instructions in memory
+
+    // Simulating fetching and executing instructions
+    for (int i = 0; i < memory.size(); ++i) {
+        cpu.fetchInstruction(memory);
+        int instruction = cpu.getIR();
+        int operand1 = (instruction & 0xFF0000) >> 16; // Extracting operands
+        int operand2 = (instruction & 0x00FF00) >> 8;
+        int operation = instruction & 0x0000FF;
+
+        // For simplicity, let's assume operations are encoded as integers
+        int result = alu.performOperation("ADD", operand1, operand2); // Assuming ADD operation
+        std::cout << "Instruction: " << instruction << ", Result: " << result << std::endl;
+    }
+
+>>>>>>> c70d70303a5d72c4a39d48491cf8e55b7bd81225
     return 0;
 }

Week 3/Register.cpp

@@ -1,5 +1,6 @@
 # Week 3: Basic CPU Components
 
+<<<<<<< HEAD
 ### 1. ALU Class
 ```cpp
 class ALU {
@@ -219,4 +220,79 @@ int main() {
     - Converts the assembly code to machine code using the `assemble` function.
     - Displays the converted machine code.
     - Displays the initial state of the registers.
-    - Loads the machine code into the
+    - Loads the machine code into the
+=======
+## Objective
+The goal of this week is to implement the core components of a CPU. This includes building the Arithmetic Logic Unit (ALU), implementing general-purpose registers, and creating the program counter and instruction register.
+
+## Program Counter and Instruction Register
+
+### Overview
+The **Program Counter (PC)** and **Instruction Register (IR)** are critical components in the design of a CPU. They work together to ensure that instructions are fetched, decoded, and executed in a sequential manner.
+
+### Program Counter (PC)
+The PC holds the memory address of the next instruction to be executed. It increments automatically after each instruction fetch, ensuring the CPU processes instructions sequentially unless a jump or branch instruction modifies the sequence.
+
+### Instruction Register (IR)
+The IR holds the currently executing instruction fetched from memory. It temporarily stores the instruction so that the CPU can decode and execute it.
+
+## Program Structure
+
+[Source Code](/Week%203/Register.cpp)
+
+## Explanation
+
+### Program Counter (PC)
+- **Initialization**: The PC is initialized to `0` in the CPU class constructor.
+- **Fetching**: In the `fetchInstruction` method, the PC points to the memory address of the next instruction.
+- **Incrementing**: After fetching an instruction, the PC is incremented to point to the next instruction.
+
+### Instruction Register (IR)
+- **Holding Instructions**: The IR holds the instruction fetched from memory.
+- **Fetching**: In the `fetchInstruction` method, the IR is set to the value of the memory at the address pointed to by the PC.
+- **Decoding and Executing**: The fetched instruction can then be decoded and executed by the CPU.
+
+### Simulated CPU Execution
+- **Memory Representation**: A vector `memory` is used to represent the instruction memory.
+- **Fetching and Storing**: The CPU fetches instructions from this memory, stores them in the IR, and increments the PC.
+- **Execution**: The ALU performs operations based on the fetched instructions, demonstrating how arithmetic and logical operations would be executed.
+
+## Arithmetic Logic Unit (ALU)
+
+The **Arithmetic Logic Unit (ALU)** is a critical component of the CPU that performs arithmetic and logic operations. It's the execution core of the CPU, where all the actual computation happens.
+
+### Key Functions of the ALU
+
+#### Arithmetic Operations
+- **Addition**: Adds two numbers.
+- **Subtraction**: Subtracts one number from another.
+- **Multiplication**: Multiplies two numbers (though sometimes handled by a separate multiplier unit).
+- **Division**: Divides one number by another (though often handled by a separate division unit).
+
+#### Logical Operations
+- **AND**: Performs a bitwise AND operation.
+- **OR**: Performs a bitwise OR operation.
+- **NOT**: Performs a bitwise NOT operation, inverting each bit.
+- **XOR**: Performs a bitwise XOR operation.
+
+#### Comparison Operations
+- **Equality**: Checks if two numbers are equal.
+- **Inequality**: Checks if two numbers are not equal.
+- **Greater Than**: Checks if one number is greater than another.
+- **Less Than**: Checks if one number is less than another.
+
+#### Shift Operations
+- **Left Shift**: Shifts bits to the left, filling with zeros.
+- **Right Shift**: Shifts bits to the right, with the option of filling with zeros (logical shift) or preserving the sign bit (arithmetic shift).
+
+### ALU Structure
+An ALU is typically composed of:
+- **Input Registers**: These hold the operands (the numbers to be operated on).
+- **Operation Decoder**: This decodes the operation to be performed (e.g., add, subtract).
+- **Arithmetic Circuitry**: Performs arithmetic operations.
+- **Logic Circuitry**: Performs logic operations.
+- **Output Register**: Holds the result of the operation.
+
+## Conclusion
+The Program Counter (PC) and Instruction Register (IR) are essential for the sequential execution of instructions in a CPU, while the ALU is responsible for performing the core computations. Together, these components form the backbone of CPU operations, enabling the execution of programs by processing instructions methodically and efficiently. This project lays the foundation for understanding how modern processors handle instruction cycles and perform computations, providing a solid base for further exploration into CPU architecture and design. 🚀
+>>>>>>> c70d70303a5d72c4a39d48491cf8e55b7bd81225