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| 1 | +From 331496883e2823184b92de1983f254f93577acc0 Mon Sep 17 00:00:00 2001 |
| 2 | +From: Rahul Rameshbabu < [email protected]> |
| 3 | +Date: Tue, 18 Nov 2025 15:20:15 -0800 |
| 4 | +Subject: [PATCH] Revert a change related to the display stack in 580.105.08 |
| 5 | + |
| 6 | +This is a clean revert to a change between 580.95.05 and 580.105.08. |
| 7 | + |
| 8 | +Signed-off-by: Rahul Rameshbabu < [email protected]> |
| 9 | +--- |
| 10 | + src/nvidia-modeset/src/nvkms-dpy.c | 23 ----------------------- |
| 11 | + src/nvidia-modeset/src/nvkms-hdmi.c | 9 +++++++++ |
| 12 | + 2 files changed, 9 insertions(+), 23 deletions(-) |
| 13 | + |
| 14 | +diff --git a/src/nvidia-modeset/src/nvkms-dpy.c b/src/nvidia-modeset/src/nvkms-dpy.c |
| 15 | +index bbdf4df50..dcbc4085a 100644 |
| 16 | +--- a/src/nvidia-modeset/src/nvkms-dpy.c |
| 17 | ++++ b/src/nvidia-modeset/src/nvkms-dpy.c |
| 18 | +@@ -909,29 +909,6 @@ void nvDpyProbeMaxPixelClock(NVDpyEvoPtr pDpyEvo) |
| 19 | + pDpyEvo->maxPixelClockKHz = |
| 20 | + ((4 * 12 * 1000 * 1000 * 16) / 18); |
| 21 | + } |
| 22 | +- } else { |
| 23 | +- const NVParsedEdidEvoRec *pParsedEdid = &pDpyEvo->parsedEdid; |
| 24 | +- |
| 25 | +- if (pParsedEdid->valid) { |
| 26 | +- const NVT_EDID_INFO *pEdidInfo = &pParsedEdid->info; |
| 27 | +- /* Default Maximum HDMI TMDS character rate is 165MHz. */ |
| 28 | +- NvU32 maxTmdsCharRate = 33; |
| 29 | +- |
| 30 | +- if (pEdidInfo->ext861.valid.H20_HF_VSDB && |
| 31 | +- (pEdidInfo->hdmiForumInfo.max_TMDS_char_rate > 0)) { |
| 32 | +- maxTmdsCharRate = |
| 33 | +- NV_MIN(pEdidInfo->hdmiForumInfo.max_TMDS_char_rate, 120); |
| 34 | +- } else if (pEdidInfo->ext861.valid.H14B_VSDB && |
| 35 | +- (pEdidInfo->hdmiLlcInfo.max_tmds_clock > 0)) { |
| 36 | +- maxTmdsCharRate = |
| 37 | +- NV_MIN(pEdidInfo->hdmiLlcInfo.max_tmds_clock, 68); |
| 38 | +- } |
| 39 | +- |
| 40 | +- /* Max Pixel Rate = Max TMDS character Rate * 5MHz */ |
| 41 | +- pDpyEvo->maxPixelClockKHz = |
| 42 | +- pDpyEvo->maxSingleLinkPixelClockKHz = |
| 43 | +- maxTmdsCharRate * 5000; |
| 44 | +- } |
| 45 | + } |
| 46 | + } else { |
| 47 | + /* |
| 48 | +diff --git a/src/nvidia-modeset/src/nvkms-hdmi.c b/src/nvidia-modeset/src/nvkms-hdmi.c |
| 49 | +index e7f2ca230..d03f0adeb 100644 |
| 50 | +--- a/src/nvidia-modeset/src/nvkms-hdmi.c |
| 51 | ++++ b/src/nvidia-modeset/src/nvkms-hdmi.c |
| 52 | +@@ -2108,6 +2108,9 @@ NvBool nvHdmiIsTmdsPossible(const NVDpyEvoRec *pDpyEvo, |
| 53 | + pDpyEvo->pDispEvo->pDevEvo->caps.hdmiTmds10BpcMaxPClkMHz * 1000UL; |
| 54 | + NvU32 adjustedMaxPixelClock = |
| 55 | + (pDpyEvo->maxSingleLinkPixelClockKHz * 4ULL) / 5ULL; |
| 56 | ++ NvU32 adjustedMaxEDIDPixelClock = |
| 57 | ++ pDpyEvo->parsedEdid.valid ? |
| 58 | ++ (pDpyEvo->parsedEdid.limits.max_pclk_10khz * 10 * 4ULL) / 5ULL : 0; |
| 59 | + |
| 60 | + /* Pixel clock must satisfy hdmiTmds10BpcMaxPClkKHz, if applicable. */ |
| 61 | + if ((hdmiTmds10BpcMaxPClkKHz > 0) && |
| 62 | +@@ -2120,6 +2123,12 @@ NvBool nvHdmiIsTmdsPossible(const NVDpyEvoRec *pDpyEvo, |
| 63 | + return FALSE; |
| 64 | + } |
| 65 | + |
| 66 | ++ /* Pixel clock must also satisfy adjustedMaxEDIDPixelClock. */ |
| 67 | ++ if (adjustedMaxEDIDPixelClock != 0 && |
| 68 | ++ pixelClock > adjustedMaxEDIDPixelClock) { |
| 69 | ++ return FALSE; |
| 70 | ++ } |
| 71 | ++ |
| 72 | + return TRUE; |
| 73 | + } |
| 74 | + |
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