From 20f46f4082910acced972cfe0c79830c54a0a286 Mon Sep 17 00:00:00 2001 From: Samuelopez-ansys Date: Mon, 7 Jul 2025 10:56:09 +0200 Subject: [PATCH 1/6] Waveport in driven terminal --- src/ansys/aedt/core/hfss.py | 7 ++++--- tests/system/general/test_20_HFSS.py | 22 +++++++++++++++------- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/src/ansys/aedt/core/hfss.py b/src/ansys/aedt/core/hfss.py index d0aa44ad5d4..6abbcd33a3a 100644 --- a/src/ansys/aedt/core/hfss.py +++ b/src/ansys/aedt/core/hfss.py @@ -7063,7 +7063,8 @@ def wave_port( self._create_pec_cap(face, assignment, dist / 10) name = self._get_unique_source_name(name, "Port") - if self.solution_type == SOLUTIONS.Hfss.DrivenModal: + # From 2024.1, wave port excitation can be assigned in Driven Terminal and Transient + if self.solution_type == SOLUTIONS.Hfss.DrivenModal or self.desktop_class.aedt_version_id >= "2024.1": if isinstance(characteristic_impedance, str): characteristic_impedance = [characteristic_impedance] * modes elif modes != len(characteristic_impedance): @@ -7071,7 +7072,7 @@ def wave_port( return self._create_waveport_driven( sheet_name, int_start, int_stop, impedance, name, renormalize, modes, deembed, characteristic_impedance ) - elif reference: + elif reference: # pragma: no cover if isinstance(sheet_name, int): faces = [sheet_name] else: @@ -7092,7 +7093,7 @@ def wave_port( impedance=impedance, terminals_rename=terminals_rename, ) - else: + else: # pragma: no cover raise AEDTRuntimeError("Reference conductors are missing.") @pyaedt_function_handler() diff --git a/tests/system/general/test_20_HFSS.py b/tests/system/general/test_20_HFSS.py index 28b3ac374bb..a346f1f8d5e 100644 --- a/tests/system/general/test_20_HFSS.py +++ b/tests/system/general/test_20_HFSS.py @@ -130,10 +130,19 @@ def test_05_create_wave_port_from_sheets(self): udp = self.aedtapp.modeler.Position(0, 0, 0) o5 = self.aedtapp.modeler.create_circle(self.aedtapp.PLANE.YZ, udp, 10, name="sheet1") self.aedtapp.solution_type = "Terminal" - outer_1 = self.aedtapp.modeler["outer_1"] - # TODO: Consider allowing a TEM port to be created. - with pytest.raises(AEDTRuntimeError, match="Reference conductors are missing."): - self.aedtapp.wave_port(o5) + coax1_len = 200 + r2 = 10.0 + coax1_origin = self.aedtapp.modeler.Position(0, 0, 0) # Thru coax origin. + outer_1 = self.aedtapp.modeler.create_cylinder( + self.aedtapp.AXIS.X, coax1_origin, r2, coax1_len, 0, "outer_1_05" + ) + coax1_len = 200 + r1 = 3.0 + coax1_origin = self.aedtapp.modeler.Position(0, 0, 0) # Thru coax origin. + + inner_1 = self.aedtapp.modeler.create_cylinder( + self.aedtapp.AXIS.X, coax1_origin, r1, coax1_len, 0, "inner_1_05" + ) port = self.aedtapp.wave_port( assignment=o5, @@ -154,9 +163,9 @@ def test_05_create_wave_port_from_sheets(self): udp = self.aedtapp.modeler.Position(80, 0, 0) o6 = self.aedtapp.modeler.create_circle(self.aedtapp.PLANE.YZ, udp, 10, name="sheet1a") - self.aedtapp.modeler.subtract(o6, "inner_1", keep_originals=True) + self.aedtapp.modeler.subtract(o6, inner_1.name, keep_originals=True) - self.aedtapp.assign_finite_conductivity(material="aluminum", assignment="inner_1") + self.aedtapp.assign_finite_conductivity(material="aluminum", assignment=inner_1.name) port = self.aedtapp.wave_port( assignment=o6, @@ -174,7 +183,6 @@ def test_05_create_wave_port_from_sheets(self): assert port.props["DoDeembed"] is False # Get the object for "outer_1". - outer_1 = self.aedtapp.modeler["outer_1"] bottom_port = self.aedtapp.wave_port( outer_1.bottom_face_z, reference=outer_1.name, create_pec_cap=True, name="bottom_probe_port" ) From 1c916e3622c34d5dbb38ca5dbf328ee353a98f9a Mon Sep 17 00:00:00 2001 From: Samuelopez-ansys Date: Mon, 7 Jul 2025 11:03:02 +0200 Subject: [PATCH 2/6] Delete exception --- tests/system/general/test_20_HFSS.py | 3 --- 1 file changed, 3 deletions(-) diff --git a/tests/system/general/test_20_HFSS.py b/tests/system/general/test_20_HFSS.py index 2964ad0208e..19b6fd5228a 100644 --- a/tests/system/general/test_20_HFSS.py +++ b/tests/system/general/test_20_HFSS.py @@ -133,9 +133,6 @@ def test_05_create_wave_port_from_sheets(self): o5 = self.aedtapp.modeler.create_circle(Plane.YZ, udp, 10, name="sheet1") self.aedtapp.solution_type = "Terminal" outer_1 = self.aedtapp.modeler["outer_1"] - # TODO: Consider allowing a TEM port to be created. - with pytest.raises(AEDTRuntimeError, match="Reference conductors are missing."): - self.aedtapp.wave_port(o5) port = self.aedtapp.wave_port( assignment=o5, From a3428064484b0319441976850a4468ab23545c27 Mon Sep 17 00:00:00 2001 From: pyansys-ci-bot <92810346+pyansys-ci-bot@users.noreply.github.com> Date: Mon, 7 Jul 2025 09:09:53 +0000 Subject: [PATCH 3/6] chore: adding changelog file 6358.added.md [dependabot-skip] --- doc/changelog.d/6358.added.md | 1 + 1 file changed, 1 insertion(+) create mode 100644 doc/changelog.d/6358.added.md diff --git a/doc/changelog.d/6358.added.md b/doc/changelog.d/6358.added.md new file mode 100644 index 00000000000..37f39707d88 --- /dev/null +++ b/doc/changelog.d/6358.added.md @@ -0,0 +1 @@ +Assign wave port in driven terminal \ No newline at end of file From 95cc97d5bff8b78b8b81fe28cf0c8df6c174d378 Mon Sep 17 00:00:00 2001 From: Samuelopez-ansys Date: Tue, 8 Jul 2025 09:39:29 +0200 Subject: [PATCH 4/6] Support Modal port (wave port and lumped) in Driven terminal --- src/ansys/aedt/core/hfss.py | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/src/ansys/aedt/core/hfss.py b/src/ansys/aedt/core/hfss.py index 5487652a34b..7d32882875a 100644 --- a/src/ansys/aedt/core/hfss.py +++ b/src/ansys/aedt/core/hfss.py @@ -6876,7 +6876,14 @@ def lumped_port( name = self._get_unique_source_name(name, "Port") - if "Modal" in self.solution_type: + if ( + self.solution_type == SolutionsHfss.DrivenModal + or ( + self.solution_type in [SolutionsHfss.DrivenTerminal, SolutionsHfss.Transient] + and self.desktop_class.aedt_version_id >= "2024.1" + ) + and not reference + ): return self._create_lumped_driven(sheet_name, point0, point1, impedance, name, renormalize, deembed) else: faces = self.modeler.get_object_faces(sheet_name) @@ -7074,8 +7081,14 @@ def wave_port( self._create_pec_cap(face, assignment, dist / 10) name = self._get_unique_source_name(name, "Port") - # From 2024.1, wave port excitation can be assigned in Driven Terminal and Transient - if self.solution_type == SolutionsHfss.DrivenModal or self.desktop_class.aedt_version_id >= "2024.1": + if ( + self.solution_type == SolutionsHfss.DrivenModal + or ( + self.solution_type in [SolutionsHfss.DrivenTerminal, SolutionsHfss.Transient] + and self.desktop_class.aedt_version_id >= "2024.1" + ) + and not reference + ): if isinstance(characteristic_impedance, str): characteristic_impedance = [characteristic_impedance] * modes elif modes != len(characteristic_impedance): @@ -7104,6 +7117,7 @@ def wave_port( impedance=impedance, terminals_rename=terminals_rename, ) + else: # pragma: no cover raise AEDTRuntimeError("Reference conductors are missing.") From 08532713023b0639b3a0fd9c2f4f0b2fae8b79fa Mon Sep 17 00:00:00 2001 From: Samuelopez-ansys Date: Thu, 10 Jul 2025 08:32:58 +0200 Subject: [PATCH 5/6] Add test --- src/ansys/aedt/core/hfss.py | 1 + tests/system/general/test_20_HFSS.py | 25 ++++++++++++++++++++++++- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/src/ansys/aedt/core/hfss.py b/src/ansys/aedt/core/hfss.py index 7d32882875a..71dcefef93a 100644 --- a/src/ansys/aedt/core/hfss.py +++ b/src/ansys/aedt/core/hfss.py @@ -377,6 +377,7 @@ def _get_unique_source_name(self, source_name, root_name): @pyaedt_function_handler(objectname="assignment", portname="port_name") def _create_lumped_driven(self, assignment, int_line_start, int_line_stop, impedance, port_name, renorm, deemb): assignment = self.modeler.convert_to_selections(assignment, True) + # TODO: Integration line should be consistent with _create_waveport_driven start = [str(i) + self.modeler.model_units for i in int_line_start] stop = [str(i) + self.modeler.model_units for i in int_line_stop] props = {} diff --git a/tests/system/general/test_20_HFSS.py b/tests/system/general/test_20_HFSS.py index 19b6fd5228a..3fb64891f7d 100644 --- a/tests/system/general/test_20_HFSS.py +++ b/tests/system/general/test_20_HFSS.py @@ -173,7 +173,6 @@ def test_05_create_wave_port_from_sheets(self): assert port.props["DoDeembed"] is False # Get the object for "outer_1". - outer_1 = self.aedtapp.modeler["outer_1"] bottom_port = self.aedtapp.wave_port( outer_1.bottom_face_z, reference=outer_1.name, create_pec_cap=True, name="bottom_probe_port" ) @@ -2019,3 +2018,27 @@ def test_boundaries_layered_impedance(self): coat4 = self.aedtapp.assign_layered_impedance([b.id, b.name, b.faces[0]], **args) assert coat4.properties["Layer 2/Material"] == "vacuum" + + def test_port_driven(self): + self.aedtapp.insert_design("hfss_wave_port") + circle = self.aedtapp.modeler.create_circle(Plane.YZ, [0, 0, 0], 10, name="sheet1") + + self.aedtapp.solution_type = "Terminal" + port = self.aedtapp.wave_port(assignment=circle) + assert port.name in self.aedtapp.excitation_names + port.delete() + + self.aedtapp.solution_type = "Eigenmode" + with pytest.raises(AEDTRuntimeError): + self.aedtapp.wave_port(assignment=circle) + + self.aedtapp.solution_type = "Modal" + start = [0.0, -10.0, 0.0] + end = [0.0, 10.0, 0.0] + port = self.aedtapp.lumped_port(assignment=circle, integration_line=[start, end]) + assert port.name in self.aedtapp.excitation_names + port.delete() + + self.aedtapp.solution_type = "Eigenmode" + with pytest.raises(AEDTRuntimeError): + self.aedtapp.lumped_port(assignment=circle) From 17f98bc54e140809483a6815057f62b1363f3ae2 Mon Sep 17 00:00:00 2001 From: Samuelopez-ansys Date: Thu, 10 Jul 2025 08:36:00 +0200 Subject: [PATCH 6/6] Fix test --- tests/system/general/test_20_HFSS.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/system/general/test_20_HFSS.py b/tests/system/general/test_20_HFSS.py index 3fb64891f7d..dfd369d3f65 100644 --- a/tests/system/general/test_20_HFSS.py +++ b/tests/system/general/test_20_HFSS.py @@ -2025,7 +2025,7 @@ def test_port_driven(self): self.aedtapp.solution_type = "Terminal" port = self.aedtapp.wave_port(assignment=circle) - assert port.name in self.aedtapp.excitation_names + assert port.name in self.aedtapp.ports port.delete() self.aedtapp.solution_type = "Eigenmode" @@ -2036,7 +2036,7 @@ def test_port_driven(self): start = [0.0, -10.0, 0.0] end = [0.0, 10.0, 0.0] port = self.aedtapp.lumped_port(assignment=circle, integration_line=[start, end]) - assert port.name in self.aedtapp.excitation_names + assert port.name in self.aedtapp.ports port.delete() self.aedtapp.solution_type = "Eigenmode"