Request for Guidance on Achieving Lowest Possible Power Consumption on PlutoSDR (Zynq 7020 + AD9361)

[whale1st]

Hi,

I am working with a PlutoSDR device based on the Zynq 7020 and AD9361.

For power saving, I currently put the AD9361 into sleep mode using:

iio_attr -d ad9361-phy ensm_mode sleep

This reduces RF front-end consumption, but I would like to further minimize the overall system power consumption.

As far as I know, PlutoSDR consists of:

1. PS (Processing System) — ARM cores, DDR, peripherals
2. PL (Programmable Logic) — FPGA fabric and logic for data paths
3. RF front-end — AD9361

My questions are:

1. Are there recommended methods to put the PS and PL into low-power or suspend states when idle?
2. Is there a way to fully power down or clock-gate the PL from the PS side when not in use?
3. Are there additional AD9361 settings beyond ensm_mode sleep that could further reduce RF power consumption (e.g., clock gating, BBPLL control, unused port shutdown)?
4. Is there any official documentation or reference design describing the lowest achievable power state for PlutoSDR, along with expected consumption numbers?

My goal is to achieve the absolute minimum power consumption when the device is idle, while still allowing quick wake-up for receive/transmit operations.

Thank you for your guidance and for the excellent work on PlutoSDR.