Skip to content

Commit 2156ac7

Browse files
PopPaul2021PopPaul2021
authored
Updates stingray next stable (#1482)
* projects/ad9081_fmca_ebz_x_band: Fix TDD sync This commit changes the following: - the RX TDD sync can be performed trough both the DO or DMAC - the clock domain crossing is performed in the DMA instead of the DO - the RX DMA LENGTH WIDTH was increased to allow large buffer captures - library/axi_dmac/data_mover: Merge changes from main Signed-off-by: PopPaul2021 <[email protected]>
1 parent 324bcf1 commit 2156ac7

File tree

2 files changed

+45
-11
lines changed

2 files changed

+45
-11
lines changed

‎library/axi_dmac/data_mover.v

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -96,28 +96,25 @@ module data_mover #(
9696
reg active = 1'b0;
9797
reg last_eot = 1'b0;
9898
reg last_non_eot = 1'b0;
99-
10099
reg needs_sync = 1'b0;
101-
wire has_sync = ~needs_sync | s_axi_sync;
102100

103-
wire s_axi_sync_valid = has_sync & s_axi_valid;
101+
wire has_sync;
104102
wire transfer_abort_s;
105-
106103
wire last_load;
107104
wire last;
108105
wire early_tlast;
109106

110107
assign xfer_req = active;
111108

112109
assign response_id = id;
113-
114110
assign source_id = id;
115111
assign source_eot = eot || early_tlast;
116-
117112
assign last = eot ? last_eot : last_non_eot;
118113

119-
assign s_axi_ready = (pending_burst & active) & ~transfer_abort_s;
120-
assign m_axi_valid = s_axi_sync_valid & s_axi_ready;
114+
assign has_sync = ~needs_sync | s_axi_sync;
115+
116+
assign s_axi_ready = (pending_burst & active) & ~transfer_abort_s & has_sync;
117+
assign m_axi_valid = s_axi_valid & s_axi_ready;
121118
assign m_axi_data = s_axi_data;
122119
assign m_axi_last = last || early_tlast;
123120
assign m_axi_partial_burst = early_tlast;

‎projects/ad9081_fmca_ebz_x_band/zcu102/system_bd.tcl

Lines changed: 39 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -157,6 +157,8 @@ ad_cpu_interrupt ps-9 mb-7 axi_spi_fmc/ip2intc_irpt
157157

158158
ad_cpu_interconnect 0x45300000 axi_spi_fmc
159159

160+
# changes on the AD9081 block design
161+
160162
# Connect TDD
161163
create_bd_port -dir I tdd_sync
162164
create_bd_port -dir O tdd_enabled
@@ -166,8 +168,43 @@ create_bd_port -dir O tdd_tx_stingray_en
166168

167169
set tdd_sync_in_net [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_tdd_0/sync_in]]]
168170
set tdd_sync_in_pin [get_bd_pins axi_tdd_0/sync_in]
169-
ad_disconnect $tdd_sync_in_net $tdd_sync_in_pin
171+
172+
set adc_do_m_axis_clk_net [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins $adc_data_offload_name/m_axis_aclk]]]
173+
set adc_do_m_axis_clk_pin [get_bd_pins $adc_data_offload_name/m_axis_aclk]
174+
175+
set adc_dma_s_axis_clk_net [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_mxfe_rx_dma/s_axis_aclk]]]
176+
set adc_dma_s_axis_clk_pin [get_bd_pins axi_mxfe_rx_dma/s_axis_aclk]
177+
178+
set adc_do_m_axis_rst_net [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins $adc_data_offload_name/m_axis_aresetn]]]
179+
set adc_do_m_axis_rst_pin [get_bd_pins $adc_data_offload_name/m_axis_aresetn]
180+
181+
set hp1_fdp_aclk_net [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins sys_ps8/saxihp1_fpd_aclk]]]
182+
set hp1_fdp_aclk_pin [get_bd_pins sys_ps8/saxihp1_fpd_aclk]
183+
184+
set axi_hp1_interconnect_aclk_net [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_hp1_interconnect/aclk]]]
185+
set axi_hp1_interconnect_aclk_pin [get_bd_pins axi_hp1_interconnect/aclk]
186+
187+
ad_disconnect $hp1_fdp_aclk_net $hp1_fdp_aclk_pin
188+
ad_disconnect $tdd_sync_in_net $tdd_sync_in_pin
189+
ad_disconnect $adc_do_m_axis_clk_net $adc_do_m_axis_clk_pin
190+
ad_disconnect $adc_dma_s_axis_clk_net $adc_dma_s_axis_clk_pin
191+
ad_disconnect $adc_do_m_axis_rst_net $adc_do_m_axis_rst_pin
192+
ad_disconnect $axi_hp1_interconnect_aclk_net $axi_hp1_interconnect_aclk_pin
193+
194+
ad_ip_parameter axi_hp1_interconnect CONFIG.NUM_CLKS 1
195+
196+
ad_connect rx_device_clk $adc_data_offload_name/m_axis_aclk
197+
ad_connect rx_device_clk axi_mxfe_rx_dma/s_axis_aclk
198+
ad_connect $sys_dma_clk sys_ps8/saxihp1_fpd_aclk
199+
ad_connect $sys_dma_clk axi_hp1_interconnect/aclk
200+
201+
ad_connect rx_device_clk_rstgen/peripheral_aresetn $adc_data_offload_name/m_axis_aresetn
202+
203+
ad_ip_parameter axi_mxfe_rx_dma CONFIG.SYNC_TRANSFER_START 1
204+
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_LENGTH_WIDTH 30
205+
170206
ad_connect axi_tdd_0/sync_in tdd_sync
207+
ad_connect axi_tdd_0/tdd_channel_1 axi_mxfe_rx_dma/s_axis_user
171208
ad_connect axi_tdd_0/tdd_channel_2 tdd_enabled
172209
ad_connect axi_tdd_0/tdd_channel_3 tdd_rx_mxfe_en
173210
ad_connect axi_tdd_0/tdd_channel_4 tdd_tx_mxfe_en

0 commit comments

Comments
 (0)