Unused signal not output in trace for cover mode

[RobertBaruch]

Two Verilog sources, one, test_case_good.v ports out a signal unf, while the other, test_case_bad.v does not. Otherwise, the logic is the same. Running a cover pass on these files passes, but looking at the traces, the vcd file for test_case_good.v shows the unf signal, while for test_case_bad.v does not contain unf at all! This is inconvenient, especially when signals are buried two or three modules deep and are unused, but are needed for debugging.

test_case.zip

Here is the diff between the sources where right=good, left=bad:

$ diff test_case_bad.v test_case_good.v
5c5
< module testcase(value, clk, rst);
---
> module testcase(value, clk, unf, rst);
17a18
>   output unf;
55c56
< module top(rst, value, clk);
---
> module top(rst, unf, value, clk);
84a86,87
>   (* src = "test_case.py:8" *)
>   output unf;
98a102
>     .unf(unf),

$ yosys -V
Yosys 0.9+932 (git sha1 10d0bad6, clang 6.0.0-1ubuntu2 -fPIC -Os)

See also: nmigen original report

Steps to reproduce the issue

• Name the file test_case_bad in test_case.sby.
• Run sby -f test_case.sby.
• Look at test_case_cover/engine_0/trace0.vcd.
• Note that unf is not present.
• Do the same for test_case_good.
• Note that unf is present.

Expected behavior

The unf signal is present in the trace provided via test_case_bad.

Actual behavior

The unf signal is not present in the trace provided via test_case_bad.

[daveshah1]

The problem is that almost all Yosys scripts (even the core built in ones like proc and prep) run opt_clean/clean to remove dangling logic; often that left behind by previous passes. This also has the effect of removing the driver of unf. One solution is to make the reg unf as (* keep *) - another more long-term option would be to keep signals and their drivers that have public names (thus were probably from user code) in conservative synthesis flows like prep.