From 5190edf87bdcbfa51edd792b87f82be4f595e3c1 Mon Sep 17 00:00:00 2001
From: MM871 <100428910+MM871@users.noreply.github.com>
Date: Sun, 30 Mar 2025 14:53:14 -0400
Subject: [PATCH 1/2] task 1 - instantiated instruction decoder in top.v

---
 CONTRIBUTORS.md |  1 +
 src/top.v       | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+)

diff --git a/CONTRIBUTORS.md b/CONTRIBUTORS.md
index ba9b207..327f2cd 100644
--- a/CONTRIBUTORS.md
+++ b/CONTRIBUTORS.md
@@ -6,3 +6,4 @@ Yuxuan Seah
 Edward Wu (edwu0029)  
 Brett(Jiaxin) Yang (brettyang02)  
 Joonseo Park (joon2022park)
+Mihir Maringanti
diff --git a/src/top.v b/src/top.v
index e69de29..fb60b82 100644
--- a/src/top.v
+++ b/src/top.v
@@ -0,0 +1,34 @@
+module InstructionDecoder(
+
+    output [6:0]  op,     
+    output [2:0]  funct3, 
+    output [6:0]  funct7, 
+    output [4:0]  rs1, 
+    output [4:0] rs2.
+    output [4:0] rd, 
+    output [24:0] extend,
+    input [31:0] instr
+
+);
+
+assign op = instr[6:0];
+assign rd = instr[11:7];
+assign funct3 = instr[14:12];
+assign rs1 = instr[19:15];
+assign rs2 = instr[24:20];
+assign funct7 = instr[31:25];
+assign extend = instr[31:7];
+
+
+InstructionDecoder instance1 (
+
+    .instr(instr),
+    .rd(rd),
+    .funct3(funct3),
+    .rs1(rs1),
+    .rs2(rs2),
+    .funct7(funct7),
+    .extend(extend)
+);
+
+endmodule
\ No newline at end of file

From 925cc8ad5b41492c09bbff7476398b585f9f3215 Mon Sep 17 00:00:00 2001
From: MM871 <100428910+MM871@users.noreply.github.com>
Date: Mon, 9 Jun 2025 18:25:28 -0400
Subject: [PATCH 2/2] Update top.v

instantiated MA and ID
---
 src/top.v | 101 +++++++++++++++++++++++++++++++++++++-----------------
 1 file changed, 69 insertions(+), 32 deletions(-)

diff --git a/src/top.v b/src/top.v
index fb60b82..dd1da0f 100644
--- a/src/top.v
+++ b/src/top.v
@@ -1,34 +1,71 @@
-module InstructionDecoder(
-
-    output [6:0]  op,     
-    output [2:0]  funct3, 
-    output [6:0]  funct7, 
-    output [4:0]  rs1, 
-    output [4:0] rs2.
-    output [4:0] rd, 
-    output [24:0] extend,
-    input [31:0] instr
-
-);
-
-assign op = instr[6:0];
-assign rd = instr[11:7];
-assign funct3 = instr[14:12];
-assign rs1 = instr[19:15];
-assign rs2 = instr[24:20];
-assign funct7 = instr[31:25];
-assign extend = instr[31:7];
-
-
-InstructionDecoder instance1 (
-
-    .instr(instr),
-    .rd(rd),
-    .funct3(funct3),
-    .rs1(rs1),
-    .rs2(rs2),
-    .funct7(funct7),
-    .extend(extend)
-);
+`include "src/types.svh"
+
+module top ( input wire clk
+           , input wire reset
+           );
+
+  wire cfsm__pc_update;
+  instr_t instr;
+
+  wire __tmp_AdrSrc
+     , __tmp_IRWrite
+     , __tmp_RegWrite
+     , __tmp_MemWrite
+     , __tmp_Branch;
+  wire [1:0] __tmp_ALUSrcA
+           , __tmp_ALUSrcB;
+  wire [2:0] __tmp_ALUOp;
+  wire [1:0] __tmp_ResultSrc;
+  wire [3:0] __tmp_FSMState;
+
+  ControlFSM control_fsm
+    ( .opcode    ( 7'b0000000      )
+    , .clk       ( clk             )
+    , .reset     ( reset           )
+    , .AdrSrc    ( __tmp_AdrSrc    )
+    , .IRWrite   ( __tmp_IRWrite   )
+    , .RegWrite  ( __tmp_RegWrite  )
+    , .PCUpdate  ( cfsm__pc_update )
+    , .MemWrite  ( __tmp_MemWrite  )
+    , .Branch    ( __tmp_Branch    )
+    , .ALUSrcA   ( __tmp_ALUSrcA   )
+    , .ALUSrcB   ( __tmp_ALUSrcB   )
+    , .ALUOp     ( __tmp_ALUOp     )
+    , .ResultSrc ( __tmp_ResultSrc )
+    , .FSMState  ( __tmp_FSMState  )
+    );
+
+  fetch fetch
+    ( .clk             ( clk             )
+    , .reset           ( reset           )
+    , .cfsm__pc_update ( cfsm__pc_update )
+    , .instr           ( instr           )
+    );
+
+  MA memory_access (
+      .A   (baseAddr),        //baseAddr is from Instruction_Decode.v it sounded like it matches with the module paramters in MA
+      .WD  (writeData),       //same as above
+      .WE  (MemWrite),        //same as above but from ControlFSM interacting with MA e.g. when memWrite = 1
+      .CLK (clk),
+      .RD  (ma__readdata)     //just left this because i dont think its connected to anything ?
+  );
+
+  Instruction_Decode instruction_decode (
+      .instr      (instr),
+      .clk        (clk),
+      .reset      (reset),
+      .ResultData (ResultData),   
+      .AdrSrc     (AdrSrc),
+      .IRWrite    (IRWrite),
+      .PCUpdate   (PCUpdate),     
+      .MemWrite   (MemWrite),
+      .Branch     (Branch),
+      .ALUSrcA    (ALUSrcA),
+      .ALUSrcB    (ALUSrcB),
+      .ResultSrc  (ResultSrc),
+      .ALUControl (ALUControl),
+      .baseAddr   (baseAddr),     
+      .writeData  (writeData)   
+  );
 
 endmodule
\ No newline at end of file