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add step top build top module
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2 files changed

+20
-7
lines changed

2 files changed

+20
-7
lines changed

.github/workflows/ci.yaml

Lines changed: 16 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
1-
name: RISC-V CI
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name: risc-v CI
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on:
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pull_request:
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jobs:
7-
test:
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build_and_test:
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runs-on: ubuntu-latest
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container:
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image: ghcr.io/utoss/risc-v:ci
@@ -13,16 +13,29 @@ jobs:
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- name: Checkout code
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uses: actions/checkout@v4
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- name: Build top
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id: build-top
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run: make build_top
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- name: Build testbench
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id: build-testbench
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run: make build_tb
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- name: Run testbench
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run: make run_tb
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- name: Upload VCD files
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uses: actions/upload-artifact@v4
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if: always()
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if: steps.build-testbench.outcome == 'success'
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with:
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name: vcd-files
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path: test/vcd/*.vcd
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retention-days: 7
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- name: Upload VVP files
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uses: actions/upload-artifact@v4
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if: steps.build-top.outcome == 'success'
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with:
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name: vvp-files
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path: out/*.vvp
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retention-days: 7

Makefile

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -12,14 +12,14 @@ TB_UTILS := test/utils.svh
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TB_VCD_BASE_PATH := test/vcd
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all: $(OUTPUT)
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build_top: $(OUTPUT)
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run_top: $(OUTPUT)
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$(VVP) $(OUTPUT)
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$(OUTPUT):
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$(IVERILOG) -g2012 -o $(OUTPUT) -c src/top.cf
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run: $(OUTPUT)
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$(VVP) $(OUTPUT)
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$(TB_OUT_PATTERN): $(TB_SRC_PATTERN) $(TB_UTILS)
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$(IVERILOG) -g2012 -o $@ -c src/top.cf $<
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