@@ -3,180 +3,180 @@ design__lint_error__count,0
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3
design__lint_timing_construct__count,0
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design__lint_warning__count,1
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design__inferred_latch__count,0
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- design__instance__count,1956
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- design__instance__area,35048 .8
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+ design__instance__count,2604
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+ design__instance__area,46916 .8
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design__instance_unmapped__count,0
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synthesis__check_error__count,0
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design__max_slew_violation__count__corner:nom_fast_1p32V_m40C,0
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11
design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C,0
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12
design__max_cap_violation__count__corner:nom_fast_1p32V_m40C,0
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- power__internal__total,0.002561003901064396
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- power__switching__total,0.0006447978084906936
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- power__leakage__total,0.000001942456037795637
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- power__total,0.0032077443320304155
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- clock__skew__worst_hold__corner:nom_fast_1p32V_m40C,-0.33760059592332753
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- clock__skew__worst_setup__corner:nom_fast_1p32V_m40C,0.35252804451195097
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- timing__hold__ws__corner:nom_fast_1p32V_m40C,0.10100059963147257
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- timing__setup__ws__corner:nom_fast_1p32V_m40C,15.186179854580764
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+ power__internal__total,0.0035878466442227364
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+ power__switching__total,0.0009364282013848424
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+ power__leakage__total,0.000001338572587883391
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+ power__total,0.004525613505393267
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+ clock__skew__worst_hold__corner:nom_fast_1p32V_m40C,-0.27209826828517947
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+ clock__skew__worst_setup__corner:nom_fast_1p32V_m40C,0.27577274577812705
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+ timing__hold__ws__corner:nom_fast_1p32V_m40C,0.0989878207420531
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+ timing__setup__ws__corner:nom_fast_1p32V_m40C,15.1259098416722
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timing__hold__tns__corner:nom_fast_1p32V_m40C,0.0
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timing__setup__tns__corner:nom_fast_1p32V_m40C,0.0
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timing__hold__wns__corner:nom_fast_1p32V_m40C,0
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24
timing__setup__wns__corner:nom_fast_1p32V_m40C,0.0
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25
timing__hold_vio__count__corner:nom_fast_1p32V_m40C,0
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- timing__hold_r2r__ws__corner:nom_fast_1p32V_m40C,0.101001
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+ timing__hold_r2r__ws__corner:nom_fast_1p32V_m40C,0.098988
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27
timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C,0
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28
timing__setup_vio__count__corner:nom_fast_1p32V_m40C,0
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- timing__setup_r2r__ws__corner:nom_fast_1p32V_m40C,17.864588
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+ timing__setup_r2r__ws__corner:nom_fast_1p32V_m40C,17.874865
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timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C,0
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design__max_slew_violation__count__corner:nom_slow_1p08V_125C,0
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design__max_fanout_violation__count__corner:nom_slow_1p08V_125C,0
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design__max_cap_violation__count__corner:nom_slow_1p08V_125C,0
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- clock__skew__worst_hold__corner:nom_slow_1p08V_125C,-0.46107571843366624
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- clock__skew__worst_setup__corner:nom_slow_1p08V_125C,0.49595418065038865
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- timing__hold__ws__corner:nom_slow_1p08V_125C,0.5845447624727732
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- timing__setup__ws__corner:nom_slow_1p08V_125C,14.384808418244118
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+ clock__skew__worst_hold__corner:nom_slow_1p08V_125C,-0.3036082859943474
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+ clock__skew__worst_setup__corner:nom_slow_1p08V_125C,0.30898159905204714
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+ timing__hold__ws__corner:nom_slow_1p08V_125C,0.5734608505929535
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+ timing__setup__ws__corner:nom_slow_1p08V_125C,14.226426661607011
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timing__hold__tns__corner:nom_slow_1p08V_125C,0.0
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timing__setup__tns__corner:nom_slow_1p08V_125C,0.0
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timing__hold__wns__corner:nom_slow_1p08V_125C,0
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timing__setup__wns__corner:nom_slow_1p08V_125C,0.0
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timing__hold_vio__count__corner:nom_slow_1p08V_125C,0
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- timing__hold_r2r__ws__corner:nom_slow_1p08V_125C,0.584545
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+ timing__hold_r2r__ws__corner:nom_slow_1p08V_125C,0.573461
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44
timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C,0
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45
timing__setup_vio__count__corner:nom_slow_1p08V_125C,0
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- timing__setup_r2r__ws__corner:nom_slow_1p08V_125C,15.266507
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+ timing__setup_r2r__ws__corner:nom_slow_1p08V_125C,15.305657
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47
timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C,0
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design__max_slew_violation__count__corner:nom_typ_1p20V_25C,0
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design__max_fanout_violation__count__corner:nom_typ_1p20V_25C,0
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50
design__max_cap_violation__count__corner:nom_typ_1p20V_25C,0
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- clock__skew__worst_hold__corner:nom_typ_1p20V_25C,-0.3841984339415616
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- clock__skew__worst_setup__corner:nom_typ_1p20V_25C,0.4080410846923666
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- timing__hold__ws__corner:nom_typ_1p20V_25C,0.28053549166616615
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- timing__setup__ws__corner:nom_typ_1p20V_25C,14.882430820058488
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+ clock__skew__worst_hold__corner:nom_typ_1p20V_25C,-0.28205841238769125
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+ clock__skew__worst_setup__corner:nom_typ_1p20V_25C,0.2881575892794197
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+ timing__hold__ws__corner:nom_typ_1p20V_25C,0.27611297363364573
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+ timing__setup__ws__corner:nom_typ_1p20V_25C,14.786535969728215
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timing__hold__tns__corner:nom_typ_1p20V_25C,0.0
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56
timing__setup__tns__corner:nom_typ_1p20V_25C,0.0
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timing__hold__wns__corner:nom_typ_1p20V_25C,0
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timing__setup__wns__corner:nom_typ_1p20V_25C,0.0
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timing__hold_vio__count__corner:nom_typ_1p20V_25C,0
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- timing__hold_r2r__ws__corner:nom_typ_1p20V_25C,0.280535
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+ timing__hold_r2r__ws__corner:nom_typ_1p20V_25C,0.276113
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timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C,0
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timing__setup_vio__count__corner:nom_typ_1p20V_25C,0
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- timing__setup_r2r__ws__corner:nom_typ_1p20V_25C,16.917490
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+ timing__setup_r2r__ws__corner:nom_typ_1p20V_25C,16.928106
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timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C,0
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65
design__max_slew_violation__count,0
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design__max_fanout_violation__count,0
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design__max_cap_violation__count,0
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- clock__skew__worst_hold,-0.33760059592332753
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- clock__skew__worst_setup,0.35252804451195097
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- timing__hold__ws,0.10100059963147257
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- timing__setup__ws,14.384808418244118
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+ clock__skew__worst_hold,-0.27209826828517947
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+ clock__skew__worst_setup,0.27577274577812705
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+ timing__hold__ws,0.0989878207420531
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+ timing__setup__ws,14.226426661607011
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timing__hold__tns,0.0
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timing__setup__tns,0.0
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timing__hold__wns,0
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timing__setup__wns,0.0
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timing__hold_vio__count,0
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- timing__hold_r2r__ws,0.101001
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+ timing__hold_r2r__ws,0.098988
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timing__hold_r2r_vio__count,0
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timing__setup_vio__count,0
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- timing__setup_r2r__ws,15.266507
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+ timing__setup_r2r__ws,15.305657
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timing__setup_r2r_vio__count,0
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design__die__bbox,0.0 0.0 202.08 313.74
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design__core__bbox,2.88 3.78 199.2 309.96
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design__io,45
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design__die__area,63400.6
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design__core__area,60109.3
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- design__instance__count__stdcell,1956
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- design__instance__area__stdcell,35048 .8
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+ design__instance__count__stdcell,2604
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+ design__instance__area__stdcell,46916 .8
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design__instance__count__macros,0
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design__instance__area__macros,0
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design__instance__count__padcells,0
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design__instance__area__padcells,0
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design__instance__count__cover,0
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design__instance__area__cover,0
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- design__instance__utilization,0.583084
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- design__instance__utilization__stdcell,0.583084
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+ design__instance__utilization,0.780525
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+ design__instance__utilization__stdcell,0.780525
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design__rows,81
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design__rows:CoreSite,81
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design__sites,33129
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design__sites:CoreSite,33129
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design__instance__count__class:buffer,8
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- design__instance__area__class:buffer,61.6896
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- design__instance__count__class:inverter,60
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- design__instance__area__class:inverter,328.406
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- design__instance__count__class:sequential_cell,309
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- design__instance__area__class:sequential_cell,14576.9
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- design__instance__count__class:multi_input_combinational_cell,919
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- design__instance__area__class:multi_input_combinational_cell,10331.2
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+ design__instance__area__class:buffer,63.504
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+ design__instance__count__class:inverter,61
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+ design__instance__area__class:inverter,332.035
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+ design__instance__count__class:sequential_cell,413
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+ design__instance__area__class:sequential_cell,19483
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+ design__instance__count__class:multi_input_combinational_cell,1268
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+ design__instance__area__class:multi_input_combinational_cell,14382.7
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flow__warnings__count,1
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flow__errors__count,0
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design__power_grid_violation__count__net:VPWR,0
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design__power_grid_violation__count__net:VGND,0
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design__power_grid_violation__count,0
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- design__instance__count__class:timing_repair_buffer,598
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- design__instance__area__class:timing_repair_buffer,9220.78
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+ design__instance__count__class:timing_repair_buffer,776
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+ design__instance__area__class:timing_repair_buffer,11978.7
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timing__drv__floating__nets,0
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timing__drv__floating__pins,0
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design__instance__displacement__total,0
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design__instance__displacement__mean,0
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design__instance__displacement__max,0
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- route__wirelength__estimated,39605
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+ route__wirelength__estimated,52272.9
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design__violations,0
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- design__instance__count__class:clock_buffer,55
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- design__instance__area__class:clock_buffer,486.259
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- design__instance__count__class:clock_inverter,2
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- design__instance__area__class:clock_inverter,16.3296
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+ design__instance__count__class:clock_buffer,65
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+ design__instance__area__class:clock_buffer,589.68
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+ design__instance__count__class:clock_inverter,10
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+ design__instance__area__class:clock_inverter,70.7616
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design__instance__count__setup_buffer,0
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- design__instance__count__hold_buffer,479
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- antenna__violating__nets,1
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- antenna__violating__pins,1
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- route__antenna_violation__count,1
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- antenna_diodes_count,5
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- design__instance__count__class:antenna_cell,5
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- design__instance__area__class:antenna_cell,27.216
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- route__net,2270
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+ design__instance__count__hold_buffer,624
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+ antenna__violating__nets,0
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+ antenna__violating__pins,0
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+ route__antenna_violation__count,0
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+ antenna_diodes_count,3
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+ design__instance__count__class:antenna_cell,3
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+ design__instance__area__class:antenna_cell,16.3296
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+ route__net,3021
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136
route__net__special,2
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- route__drc_errors__iter:0,539
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- route__wirelength__iter:0,41337
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- route__drc_errors__iter:1,187
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- route__wirelength__iter:1,41058
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- route__drc_errors__iter:2,180
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- route__wirelength__iter:2,40996
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- route__drc_errors__iter:3,33
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- route__wirelength__iter:3,40928
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- route__drc_errors__iter:4,10
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- route__wirelength__iter:4,40922
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+ route__drc_errors__iter:0,762
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+ route__wirelength__iter:0,54956
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+ route__drc_errors__iter:1,241
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+ route__wirelength__iter:1,54449
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+ route__drc_errors__iter:2,176
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+ route__wirelength__iter:2,54320
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+ route__drc_errors__iter:3,13
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+ route__wirelength__iter:3,54208
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+ route__drc_errors__iter:4,5
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+ route__wirelength__iter:4,54198
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route__drc_errors__iter:5,0
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- route__wirelength__iter:5,40903
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+ route__wirelength__iter:5,54191
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route__drc_errors,0
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- route__wirelength,40903
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- route__vias,10879
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- route__vias__singlecut,10879
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+ route__wirelength,54191
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+ route__vias,14499
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+ route__vias__singlecut,14499
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153
route__vias__multicut,0
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design__disconnected_pin__count,14
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design__critical_disconnected_pin__count,0
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- route__wirelength__max,387.635
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- timing__unannotated_net__count__corner:nom_fast_1p32V_m40C,332
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+ route__wirelength__max,527.185
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+ timing__unannotated_net__count__corner:nom_fast_1p32V_m40C,439
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timing__unannotated_net_filtered__count__corner:nom_fast_1p32V_m40C,0
159
- timing__unannotated_net__count__corner:nom_slow_1p08V_125C,332
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+ timing__unannotated_net__count__corner:nom_slow_1p08V_125C,439
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timing__unannotated_net_filtered__count__corner:nom_slow_1p08V_125C,0
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- timing__unannotated_net__count__corner:nom_typ_1p20V_25C,332
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+ timing__unannotated_net__count__corner:nom_typ_1p20V_25C,439
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timing__unannotated_net_filtered__count__corner:nom_typ_1p20V_25C,0
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- timing__unannotated_net__count,332
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+ timing__unannotated_net__count,439
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timing__unannotated_net_filtered__count,0
165
- design_powergrid__voltage__worst__net:VPWR__corner:nom_typ_1p20V_25C,1.19997
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- design_powergrid__drop__average__net:VPWR__corner:nom_typ_1p20V_25C,1.19998
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- design_powergrid__drop__worst__net:VPWR__corner:nom_typ_1p20V_25C,0.0000319743
168
- design_powergrid__voltage__worst__net:VGND__corner:nom_typ_1p20V_25C,0.0000344539
169
- design_powergrid__drop__average__net:VGND__corner:nom_typ_1p20V_25C,0.0000184762
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- design_powergrid__drop__worst__net:VGND__corner:nom_typ_1p20V_25C,0.0000344539
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- design_powergrid__voltage__worst,0.0000344539
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- design_powergrid__voltage__worst__net:VPWR,1.19997
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- design_powergrid__drop__worst,0.0000344539
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- design_powergrid__drop__worst__net:VPWR,0.0000319743
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- design_powergrid__voltage__worst__net:VGND,0.0000344539
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- design_powergrid__drop__worst__net:VGND,0.0000344539
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+ design_powergrid__voltage__worst__net:VPWR__corner:nom_typ_1p20V_25C,1.19996
166
+ design_powergrid__drop__average__net:VPWR__corner:nom_typ_1p20V_25C,1.19997
167
+ design_powergrid__drop__worst__net:VPWR__corner:nom_typ_1p20V_25C,0.000041372
168
+ design_powergrid__voltage__worst__net:VGND__corner:nom_typ_1p20V_25C,0.0000403386
169
+ design_powergrid__drop__average__net:VGND__corner:nom_typ_1p20V_25C,0.0000275487
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+ design_powergrid__drop__worst__net:VGND__corner:nom_typ_1p20V_25C,0.0000403386
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+ design_powergrid__voltage__worst,0.0000403386
172
+ design_powergrid__voltage__worst__net:VPWR,1.19996
173
+ design_powergrid__drop__worst,0.000041372
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+ design_powergrid__drop__worst__net:VPWR,0.000041372
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+ design_powergrid__voltage__worst__net:VGND,0.0000403386
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+ design_powergrid__drop__worst__net:VGND,0.0000403386
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ir__voltage__worst,1.1999999999999999555910790149937383830547332763671875
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- ir__drop__avg,0.000019499999999999999646983772638719756287173368036746978759765625
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- ir__drop__worst,0.0000319999999999999985519395784283602779396460391581058502197265625
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+ ir__drop__avg,0.00002799999999999999957998007837911558226551278494298458099365234375
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+ ir__drop__worst,0.0000413999999999999966442641718966655162148526869714260101318359375
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180
magic__drc_error__count,0
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181
magic__illegal_overlap__count,0
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182
design__lvs_device_difference__count,0
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