set up generic testbench targets in Makefile

Author: TheDeepestSpace

.gitignore

@@ -1,7 +1,3 @@
 *.vvp
-*.vcd
-
-!test/fetch_tb.vcd
-!test/beq_tb.vcd
 
 .devcontainer/

Makefile

@@ -3,19 +3,45 @@ OUTPUT 	 := out/top.vvp
 IVERILOG := iverilog
 VVP 		 := vvp
 
+TB_SRC_PATTERN := test/%_tb.sv
+TB_OUT_PATTERN := out/%_tb.vvp
+
+TB_SRCS := $(wildcard $(subst %,*,$(TB_SRC_PATTERN)))
+TB_VVPS := $(patsubst $(TB_SRC_PATTERN),$(TB_OUT_PATTERN),$(TB_SRCS))
+TB_UTILS := test/utils.svh
+
+TB_VCD_BASE_PATH := test/vcd
+
 all: $(OUTPUT)
 
-$(OUTPUT): $(SRCS)
+$(OUTPUT):
 	$(IVERILOG) -g2012 -o $(OUTPUT) -c src/top.cf
 
 run: $(OUTPUT)
 	$(VVP) $(OUTPUT)
 
-# tmp
-fetch_tb:
-	$(IVERILOG) -g2012 -o $(OUTPUT) $(SRCS) -c src/top.cf test/fetch_tb.sv
+$(TB_OUT_PATTERN): $(TB_SRC_PATTERN) $(TB_UTILS)
+	$(IVERILOG) -g2012 -o $@ -c src/top.cf $<
+
+build_tb: $(TB_VVPS)
 
-beq_tb:
-	$(IVERILOG) -g2012 -o $(OUTPUT) $(SRCS) -c src/top.cf test/beq_tb.sv
+run_tb: $(TB_VVPS)
+	@failed=0;                                                \
+	for tb in $(TB_VVPS); do                                  \
+		echo "Running $$tb...";                                 \
+		if ! $(VVP) -N $$tb +VCD_PATH=$(TB_VCD_BASE_PATH); then \
+			echo "\033[31mFAILED: $$tb\033[0m";                   \
+			failed=1;                                             \
+		else                                                    \
+			echo "\033[32mPASSED: $$tb\033[0m";                   \
+		fi;                                                     \
+		echo "";                                                \
+	done;                                                     \
+	if [ $$failed -eq 1 ]; then                               \
+		echo "\033[31mSome testbenches failed!\033[0m";         \
+		exit 1;                                                 \
+	else                                                      \
+		echo "\033[32mAll testbenches passed!\033[0m";          \
+	fi
 
-.PHONY: all run
+.PHONY: all run testbenches run-tests

test/beq_tb.sv

@@ -3,6 +3,8 @@
 `include "src/utils.svh"
 `include "src/types.svh"
 
+`include "test/utils.svh"
+
 module beq_tb;
   reg clk;
   reg reset;
@@ -110,8 +112,6 @@ module beq_tb;
     $finish;
   end
 
-  initial begin
-    $dumpfile("test/beq_tb.vcd");
-    $dumpvars(0, beq_tb);
-  end
+  `SETUP_VCD_DUMP(beq_tb)
+
 endmodule

test/fetch_tb.sv

@@ -3,6 +3,8 @@
 `include "src/utils.svh"
 `include "src/types.svh"
 
+`include "test/utils.svh"
+
 module fetch_tb;
 
   reg     clk;
@@ -184,8 +186,6 @@ module fetch_tb;
     $finish;
   end
 
-  initial begin
-    $dumpfile("test/fetch_tb.vcd");
-    $dumpvars(0, fetch_tb);
-  end
+  `SETUP_VCD_DUMP(fetch_tb)
+
 endmodule

test/utils.svh

@@ -0,0 +1,21 @@
+`ifndef TEST__UTILS_SVH
+`define TEST__UTILS_SVH
+
+`define SETUP_VCD_DUMP(module_name)                                     \
+  initial begin                                                         \
+    string vcd_path;                                                    \
+    string vcd_filename;                                                \
+                                                                        \
+    if ($test$plusargs("VCD_PATH")) begin                               \
+      if ($value$plusargs("VCD_PATH=%s", vcd_path) == 0) begin          \
+        $display("VCD_PATH not set, not dumping VCD");                  \
+      end                                                               \
+                                                                        \
+      vcd_filename = $sformatf("%s/%s.vcd", vcd_path, `"module_name`"); \
+                                                                        \
+      $dumpfile(vcd_filename);                                          \
+      $dumpvars(0, module_name);                                        \
+    end                                                                 \
+  end
+
+`endif

test/vcd/.gitkeep

@@ -1,5 +1,5 @@
 $date
-	Thu Jun  5 04:15:59 2025
+	Sun Jun 15 20:29:55 2025
 $end
 $version
 	Icarus Verilog
@@ -125,6 +125,8 @@ $var reg 32 o writeData [31:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
+$scope begin $unm_blk_47 $end
+$upscope $end
 $upscope $end
 $enddefinitions $end
 $comment Show the parameter values. $end

test/beq_tb.vcd renamed to test/vcd/beq_tb.vcd

@@ -1,5 +1,5 @@
 $date
-	Thu Jun  5 04:15:54 2025
+	Sun Jun 15 20:29:55 2025
 $end
 $version
 	Icarus Verilog
@@ -35,6 +35,8 @@ $upscope $end
 $scope begin $ivl_for_loop0 $end
 $var integer 32 0 i [31:0] $end
 $upscope $end
+$scope begin $unm_blk_48 $end
+$upscope $end
 $upscope $end
 $enddefinitions $end
 $comment Show the parameter values. $end