diff --git a/flow/designs/rapidus2hp/ethmac/constraint.sdc b/flow/designs/rapidus2hp/ethmac/constraint.sdc index a4037db532..50e470ebba 100644 --- a/flow/designs/rapidus2hp/ethmac/constraint.sdc +++ b/flow/designs/rapidus2hp/ethmac/constraint.sdc @@ -4,28 +4,36 @@ set clk_io_pct 0.2 set clk_port [get_ports $top_clk_name] create_clock -name $top_clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs] +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $top_clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $top_clk_name \ + [all_outputs] set tx_clk_name mtx_clk_pad_i set tx_clk_port [get_ports $tx_clk_name] set tx_clk_period 300 create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port -set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port] -set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs -set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs] +set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \ + $tx_clk_port] +set_input_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \ + $mtx_non_clock_inputs +set_output_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \ + [all_outputs] set rx_clk_name mrx_clk_pad_i set rx_clk_port [get_ports $rx_clk_name] set rx_clk_period 300 create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port -set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port] -set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs -set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs] +set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \ + $rx_clk_port] +set_input_delay [expr { $rx_clk_period * $clk_io_pct }] -clock $rx_clk_name \ + $mrx_non_clock_inputs +set_output_delay [expr { $rx_clk_period * $clk_io_pct }] -clock $rx_clk_name \ + [all_outputs] set_clock_groups -name core_clock -logically_exclusive \ - -group [get_clocks $top_clk_name] \ - -group [get_clocks $tx_clk_name] \ - -group [get_clocks $rx_clk_name] + -group [get_clocks $top_clk_name] \ + -group [get_clocks $tx_clk_name] \ + -group [get_clocks $rx_clk_name] set_max_fanout 10 [current_design] diff --git a/flow/designs/rapidus2hp/gcd/constraint.sdc b/flow/designs/rapidus2hp/gcd/constraint.sdc index fd5cb2c47b..3eb0db2391 100644 --- a/flow/designs/rapidus2hp/gcd/constraint.sdc +++ b/flow/designs/rapidus2hp/gcd/constraint.sdc @@ -1,15 +1,17 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk set clk_period 185 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] diff --git a/flow/designs/rapidus2hp/hercules_is_int/prects.sdc b/flow/designs/rapidus2hp/hercules_is_int/prects.sdc index 0444b6a48e..934de6be54 100644 --- a/flow/designs/rapidus2hp/hercules_is_int/prects.sdc +++ b/flow/designs/rapidus2hp/hercules_is_int/prects.sdc @@ -8,7 +8,5 @@ set_max_fanout 32 [current_design] set_load 10 [all_outputs] set_max_capacitance 10 [all_inputs] -create_clock -name "clk" -add -period $clk_period -waveform [list 0.0 [expr 0.5*$clk_period]] [get_ports clk] - - - +create_clock -name "clk" -add -period $clk_period \ + -waveform [list 0.0 [expr { 0.5 * $clk_period }]] [get_ports clk] diff --git a/flow/designs/rapidus2hp/ibex/constraint.sdc b/flow/designs/rapidus2hp/ibex/constraint.sdc index 4ce87915ab..1465ae6069 100644 --- a/flow/designs/rapidus2hp/ibex/constraint.sdc +++ b/flow/designs/rapidus2hp/ibex/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 790 set clk_io_pct 0.2 @@ -9,5 +9,7 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] diff --git a/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc b/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc index 7d9d39b7c1..d714d428ae 100644 --- a/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc +++ b/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc @@ -1,4 +1,4 @@ -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 1468 set clk_io_pct 0.2 @@ -9,5 +9,7 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] diff --git a/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc index 6b6ad12acf..9f0d6c6a9b 100644 --- a/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc +++ b/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 425 set clk_io_pct 0.2 @@ -11,5 +11,7 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs]