diff --git a/flow/designs/asap7/aes-block/constraint.sdc b/flow/designs/asap7/aes-block/constraint.sdc index 8256fd752b..8d7d7c5987 100644 --- a/flow/designs/asap7/aes-block/constraint.sdc +++ b/flow/designs/asap7/aes-block/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes-mbff/constraint.sdc b/flow/designs/asap7/aes-mbff/constraint.sdc index f5bce962e5..a9b5a65d9c 100644 --- a/flow/designs/asap7/aes-mbff/constraint.sdc +++ b/flow/designs/asap7/aes-mbff/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes/constraint.sdc b/flow/designs/asap7/aes/constraint.sdc index f5bce962e5..a9b5a65d9c 100644 --- a/flow/designs/asap7/aes/constraint.sdc +++ b/flow/designs/asap7/aes/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes_lvt/constraint.sdc b/flow/designs/asap7/aes_lvt/constraint.sdc index f5bce962e5..a9b5a65d9c 100644 --- a/flow/designs/asap7/aes_lvt/constraint.sdc +++ b/flow/designs/asap7/aes_lvt/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/ethmac/constraint.sdc b/flow/designs/asap7/ethmac/constraint.sdc index 43759e0718..1dd0000a50 100644 --- a/flow/designs/asap7/ethmac/constraint.sdc +++ b/flow/designs/asap7/ethmac/constraint.sdc @@ -3,7 +3,7 @@ set clk_period 1000 set clk_io_pct 0.2 set clk_port [get_ports $top_clk_name] create_clock -name $top_clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs] diff --git a/flow/designs/asap7/ethmac_lvt/constraint.sdc b/flow/designs/asap7/ethmac_lvt/constraint.sdc index 6d59823cb6..465d603d0c 100644 --- a/flow/designs/asap7/ethmac_lvt/constraint.sdc +++ b/flow/designs/asap7/ethmac_lvt/constraint.sdc @@ -3,7 +3,7 @@ set clk_period 1000 set clk_io_pct 0.2 set clk_port [get_ports $top_clk_name] create_clock -name $top_clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs] diff --git a/flow/designs/asap7/gcd/constraint.sdc b/flow/designs/asap7/gcd/constraint.sdc index dc5d070adf..27de11250b 100644 --- a/flow/designs/asap7/gcd/constraint.sdc +++ b/flow/designs/asap7/gcd/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/ibex/constraint.sdc b/flow/designs/asap7/ibex/constraint.sdc index 956a60e40e..30bb0a2292 100644 --- a/flow/designs/asap7/ibex/constraint.sdc +++ b/flow/designs/asap7/ibex/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/ibex/constraint_pos_slack.sdc b/flow/designs/asap7/ibex/constraint_pos_slack.sdc index 0627af5b19..d605a5aa8e 100644 --- a/flow/designs/asap7/ibex/constraint_pos_slack.sdc +++ b/flow/designs/asap7/ibex/constraint_pos_slack.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc index 3800daaf8b..bd163e05ff 100644 --- a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc +++ b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc index 2e77403245..d1aa7a70f9 100644 --- a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc +++ b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/mock-alu/constraints.sdc b/flow/designs/asap7/mock-alu/constraints.sdc index 66d1e5725e..dd93e54e87 100644 --- a/flow/designs/asap7/mock-alu/constraints.sdc +++ b/flow/designs/asap7/mock-alu/constraints.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/riscv32i/constraint.sdc b/flow/designs/asap7/riscv32i/constraint.sdc index 3cea613851..9868986799 100644 --- a/flow/designs/asap7/riscv32i/constraint.sdc +++ b/flow/designs/asap7/riscv32i/constraint.sdc @@ -9,6 +9,6 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/swerv_wrapper/constraint.sdc b/flow/designs/asap7/swerv_wrapper/constraint.sdc index 955b0805d5..2cae11c882 100644 --- a/flow/designs/asap7/swerv_wrapper/constraint.sdc +++ b/flow/designs/asap7/swerv_wrapper/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/uart/constraint.sdc b/flow/designs/asap7/uart/constraint.sdc index 0d7aa226f0..b58ae3408f 100644 --- a/flow/designs/asap7/uart/constraint.sdc +++ b/flow/designs/asap7/uart/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf12/aes/constraint.sdc b/flow/designs/gf12/aes/constraint.sdc index ae1bc48d58..a820710ab4 100644 --- a/flow/designs/gf12/aes/constraint.sdc +++ b/flow/designs/gf12/aes/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf12/gcd/constraint.sdc b/flow/designs/gf12/gcd/constraint.sdc index 18fe09d581..d7ee23ad0a 100644 --- a/flow/designs/gf12/gcd/constraint.sdc +++ b/flow/designs/gf12/gcd/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf12/ibex/constraint.sdc b/flow/designs/gf12/ibex/constraint.sdc index 3d19120721..85d691d76e 100644 --- a/flow/designs/gf12/ibex/constraint.sdc +++ b/flow/designs/gf12/ibex/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf12/jpeg/constraint.sdc b/flow/designs/gf12/jpeg/constraint.sdc index d196f8f423..9e32a57bf1 100644 --- a/flow/designs/gf12/jpeg/constraint.sdc +++ b/flow/designs/gf12/jpeg/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf12/tinyRocket/constraint.sdc b/flow/designs/gf12/tinyRocket/constraint.sdc index 02e8f6f066..79e26f0bee 100644 --- a/flow/designs/gf12/tinyRocket/constraint.sdc +++ b/flow/designs/gf12/tinyRocket/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/aes/constraint.sdc b/flow/designs/gf180/aes/constraint.sdc index da8e0a8244..9efd6867db 100644 --- a/flow/designs/gf180/aes/constraint.sdc +++ b/flow/designs/gf180/aes/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/ibex/constraint.sdc b/flow/designs/gf180/ibex/constraint.sdc index d91411c4dc..24711119f1 100644 --- a/flow/designs/gf180/ibex/constraint.sdc +++ b/flow/designs/gf180/ibex/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/jpeg/constraint.sdc b/flow/designs/gf180/jpeg/constraint.sdc index 5862d8ce02..42d6b4abf9 100644 --- a/flow/designs/gf180/jpeg/constraint.sdc +++ b/flow/designs/gf180/jpeg/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/riscv32i/constraint.sdc b/flow/designs/gf180/riscv32i/constraint.sdc index e38107b41f..3b2184da75 100644 --- a/flow/designs/gf180/riscv32i/constraint.sdc +++ b/flow/designs/gf180/riscv32i/constraint.sdc @@ -7,6 +7,6 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/uart-blocks/constraint.sdc b/flow/designs/gf180/uart-blocks/constraint.sdc index 5c231242df..e4bcee59d1 100644 --- a/flow/designs/gf180/uart-blocks/constraint.sdc +++ b/flow/designs/gf180/uart-blocks/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc index 5c231242df..e4bcee59d1 100644 --- a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc +++ b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/aes/constraint.sdc b/flow/designs/ihp-sg13g2/aes/constraint.sdc index f32c9be836..f0b3b99355 100644 --- a/flow/designs/ihp-sg13g2/aes/constraint.sdc +++ b/flow/designs/ihp-sg13g2/aes/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/gcd/constraint.sdc b/flow/designs/ihp-sg13g2/gcd/constraint.sdc index 20c0c7a73e..0c1e6d1d5b 100644 --- a/flow/designs/ihp-sg13g2/gcd/constraint.sdc +++ b/flow/designs/ihp-sg13g2/gcd/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/ibex/constraint.sdc b/flow/designs/ihp-sg13g2/ibex/constraint.sdc index 979e0b0b28..fed426995f 100644 --- a/flow/designs/ihp-sg13g2/ibex/constraint.sdc +++ b/flow/designs/ihp-sg13g2/ibex/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc index 923cf1199f..0ca3cc5b3d 100644 --- a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc +++ b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/spi/constraint.sdc b/flow/designs/ihp-sg13g2/spi/constraint.sdc index 225f73938c..956369e4b8 100644 --- a/flow/designs/ihp-sg13g2/spi/constraint.sdc +++ b/flow/designs/ihp-sg13g2/spi/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/aes/constraint.sdc b/flow/designs/nangate45/aes/constraint.sdc index d7b8414c8e..95f709e341 100644 --- a/flow/designs/nangate45/aes/constraint.sdc +++ b/flow/designs/nangate45/aes/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/gcd/constraint.sdc b/flow/designs/nangate45/gcd/constraint.sdc index 852fef6395..c6d4b902be 100644 --- a/flow/designs/nangate45/gcd/constraint.sdc +++ b/flow/designs/nangate45/gcd/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/ibex/constraint.sdc b/flow/designs/nangate45/ibex/constraint.sdc index 210d591716..38667319ac 100644 --- a/flow/designs/nangate45/ibex/constraint.sdc +++ b/flow/designs/nangate45/ibex/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/jpeg/constraint.sdc b/flow/designs/nangate45/jpeg/constraint.sdc index 4548cad10c..7c97d6490a 100644 --- a/flow/designs/nangate45/jpeg/constraint.sdc +++ b/flow/designs/nangate45/jpeg/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/swerv/constraint.sdc b/flow/designs/nangate45/swerv/constraint.sdc index be7426a1a2..ccaab11ddf 100644 --- a/flow/designs/nangate45/swerv/constraint.sdc +++ b/flow/designs/nangate45/swerv/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/swerv_wrapper/constraint.sdc b/flow/designs/nangate45/swerv_wrapper/constraint.sdc index 4ccc054acb..f7c9f08b64 100644 --- a/flow/designs/nangate45/swerv_wrapper/constraint.sdc +++ b/flow/designs/nangate45/swerv_wrapper/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/aes/constraint.sdc b/flow/designs/sky130hd/aes/constraint.sdc index f32c9be836..f0b3b99355 100644 --- a/flow/designs/sky130hd/aes/constraint.sdc +++ b/flow/designs/sky130hd/aes/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/chameleon/constraint.sdc b/flow/designs/sky130hd/chameleon/constraint.sdc index da65f16f66..d3a0d6df47 100644 --- a/flow/designs/sky130hd/chameleon/constraint.sdc +++ b/flow/designs/sky130hd/chameleon/constraint.sdc @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/gcd/constraint.sdc b/flow/designs/sky130hd/gcd/constraint.sdc index d3fcca89a9..fadfedd028 100644 --- a/flow/designs/sky130hd/gcd/constraint.sdc +++ b/flow/designs/sky130hd/gcd/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/ibex/constraint.sdc b/flow/designs/sky130hd/ibex/constraint.sdc index 979e0b0b28..fed426995f 100644 --- a/flow/designs/sky130hd/ibex/constraint.sdc +++ b/flow/designs/sky130hd/ibex/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/jpeg/constraint.sdc b/flow/designs/sky130hd/jpeg/constraint.sdc index 5ac34a1acf..5d9b007f0e 100644 --- a/flow/designs/sky130hd/jpeg/constraint.sdc +++ b/flow/designs/sky130hd/jpeg/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/aes/constraint.sdc b/flow/designs/sky130hs/aes/constraint.sdc index f99ac98b46..5878fa7782 100644 --- a/flow/designs/sky130hs/aes/constraint.sdc +++ b/flow/designs/sky130hs/aes/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/gcd/constraint.sdc b/flow/designs/sky130hs/gcd/constraint.sdc index 71ddb64d28..ed93d8a1eb 100644 --- a/flow/designs/sky130hs/gcd/constraint.sdc +++ b/flow/designs/sky130hs/gcd/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/ibex/constraint.sdc b/flow/designs/sky130hs/ibex/constraint.sdc index a844a0dba6..9927412616 100644 --- a/flow/designs/sky130hs/ibex/constraint.sdc +++ b/flow/designs/sky130hs/ibex/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/jpeg/constraint.sdc b/flow/designs/sky130hs/jpeg/constraint.sdc index d150e21e15..4c40fe5a3f 100644 --- a/flow/designs/sky130hs/jpeg/constraint.sdc +++ b/flow/designs/sky130hs/jpeg/constraint.sdc @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/platforms/asap7/constraints.sdc b/flow/platforms/asap7/constraints.sdc index b08b9fa596..db9965aba7 100644 --- a/flow/platforms/asap7/constraints.sdc +++ b/flow/platforms/asap7/constraints.sdc @@ -69,7 +69,7 @@ set sdc_version 2.0 set clk_port [get_ports $clk_port_name] create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port -set non_clk_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clk_inputs [all_inputs -no_clocks] set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}] # Optimization targets: overconstrain by default and