Merge pull request #3300 from luarss/topic/tclint-4

Tclint 4

Author: maliberty

flow/designs/nangate45/bp_quad/bsg_chip.sdc

@@ -144,5 +144,4 @@ set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_8_i]
 set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_8_i]
 set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_8_i]
 set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_8_i]
-set_timing_derate -early -cell_delay 0.97 [get_cells \
-  {bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}]
+set_timing_derate -early -cell_delay 0.97 [get_cells {bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}] ;# tclint-disable-line line-length

flow/platforms/asap7/constraints.sdc

@@ -1,14 +1,14 @@
 # A minimal generic constraints.sdc for architectural exploration of macros
 # -------------------------------------------------------------------------
-# 
+#
 # Used in designs/asap7/mock-array, for example.
 #
 # From the following observations, all else follows: the only thing
 # that can fail timing closure, is a register to register path. All
 # other constraints give the flow an optimization target. Failure
 # to meet the timing constraint of an optimization target constraint
 # is not a timing closure failure.
-# 
+#
 # Note that ORFS regression checks do not have the ability to distinguish
 # between timing closure failures(register to register paths) and
 # optimization constraints violations.
@@ -17,26 +17,26 @@
 # in mock-array Element, such as maximum transit time for a combinational path
 # through mock-array Element, may or may not cause timing
 # violations later on higher up in mock-array on register to register paths.
-# 
+#
 # For the Element, the only register to register path
 # are within the Element and no lower level macros are
 # involved. Register to register paths within Element have to be checked
 # at the Element level as they are invisible higher up in mock-array.
-# 
+#
 # As for the remaining optimization constraints for Element, they
 # should be for combinational through paths(io-io) and
 # from input pins to register(io-reg) and from register to output pins(reg-io):
-# 
+#
 # This constraints.sdc file is designed such that the clock latency & tree
 # can be ignored as far constraints go;
 # it is not part of the optimization constraints. The clock tree latency
 # is accounted for in register to register paths and not visible outside
 # of the macro that use this constraints.sdc.
-# 
+#
 # All non reg-reg paths in Element are part of reg-reg paths in mock-array
 # and timing closure in which those take part are checked at the mock-array
 # level.
-# 
+#
 # With this in mind, the constraints.sdc file for the Element becomes
 # quite general and simple. set_max_delay is used exclusively for
 # optimization constraints and the clock period is used to check timing
@@ -51,13 +51,13 @@
 # the time at the clock pin for the macro, which makes it impossible to articulate
 # the number that is passed in to set_input/output_delay without taking
 # clock network insertion latency into account.
-# 
+#
 # Since set_input_delay is not used and set_max_delay is used instead, then
 # no hold cells are inserted, which is what is desired here.
 #
 # Details such as clock uncertainty, max transition time, load, etc.
 # is beyond the scope of this generic constraints.sdc file.
-# 
+#
 # Beware of [path segmentation](https://docs.xilinx.com/r/2020.2-English/ug906-vivado-design-analysis/TIMING-13-Timing-Paths-Ignored-Due-to-Path-Segmentation), which
 # can occur with OpenSTA.
 
@@ -76,9 +76,12 @@ set non_clk_inputs [all_inputs -no_clocks]
 #
 # Minimum time for io-io, io-reg, reg-io paths in macro is on
 # the order of 80ps for a small macro on ASAP7.
-set_max_delay [expr { [info exists in2reg_max] ? $in2reg_max : 80 }] -from $non_clk_inputs -to [all_registers]
-set_max_delay [expr { [info exists reg2out_max] ? $reg2out_max : 80 }] -from [all_registers] -to [all_outputs]
-set_max_delay [expr { [info exists in2out_max] ? $in2out_max : 80 }] -from $non_clk_inputs -to [all_outputs]
+set_max_delay [expr { [info exists in2reg_max] ? $in2reg_max : 80 }] -from $non_clk_inputs \
+  -to [all_registers]
+set_max_delay [expr { [info exists reg2out_max] ? $reg2out_max : 80 }] -from [all_registers] \
+  -to [all_outputs]
+set_max_delay [expr { [info exists in2out_max] ? $in2out_max : 80 }] -from $non_clk_inputs \
+  -to [all_outputs]
 
 # This allows us to view the different groups
 # in the histogram in the GUI and also includes these

flow/platforms/asap7/liberty_suppressions.tcl

@@ -1,4 +1,5 @@
 # To remove [WARNING STA-1212] from the logs for ASAP7.
-# /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 13178, timing group from output port.
+# /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz
+#   line 13178, timing group from output port.
 # Added following suppress_message
 suppress_message STA 1212

flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl

@@ -18,10 +18,13 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
 define_pdn_grid -name {top} -voltage_domains {CORE}
 add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins
 add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins
-add_pdn_ring -grid {top} -layers {M5 M6} -widths {0.504 0.544} -spacings {0.096} -core_offset {0.504}
+add_pdn_ring -grid {top} -layers {M5 M6} -widths {0.504 0.544} -spacings {0.096} \
+  -core_offset {0.504}
 
-add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.16} -offset {1.50} -extend_to_core_ring
-add_pdn_stripe -grid {top} -layer {M6} -width {0.288} -spacing {0.096} -pitch {4.32} -offset {1.504} -extend_to_core_ring
+add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.16} \
+  -offset {1.50} -extend_to_core_ring
+add_pdn_stripe -grid {top} -layer {M6} -width {0.288} -spacing {0.096} -pitch {4.32} \
+  -offset {1.504} -extend_to_core_ring
 
 add_pdn_connect -grid {top} -layers {M1 M2}
 add_pdn_connect -grid {top} -layers {M2 M5}
@@ -40,8 +43,10 @@ foreach macro [find_macros] {
 }
 set macro_names [dict keys $macro_names]
 
+set halo_x $::env(MACRO_ROWS_HALO_X)
+set halo_y $::env(MACRO_ROWS_HALO_Y)
 define_pdn_grid -macro -cells $macro_names \
-  -halo "$::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y) $::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y)" \
+  -halo "$halo_x $halo_y $halo_x $halo_y" \
   -voltage_domains {CORE} -name ElementGrid
 
 add_pdn_connect -grid {ElementGrid} -layers {M5 M6}

flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl

@@ -25,7 +25,8 @@ add_pdn_ring -grid {top} -layers {M5 M4} -widths {0.12 0.12} -spacings {0.072} -
 add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins
 add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins
 
-add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} -extend_to_core_ring
+add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} \
+  -extend_to_core_ring
 
 add_pdn_connect -grid {top} -layers {M1 M2}
 add_pdn_connect -grid {top} -layers {M2 M5}

flow/platforms/asap7/openRoad/pdn/grid_strategy-M1-M2-M5-M6.tcl

@@ -28,10 +28,12 @@ add_pdn_connect -grid {top} -layers {M5 M6}
 ####################################
 # grid for: CORE_macro_grid_1
 ####################################
-define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -cells {.*}
+define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro \
+  -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -cells {.*}
 add_pdn_connect -grid {CORE_macro_grid_1} -layers {M4 M5}
 ####################################
 # grid for: CORE_macro_grid_2
 ####################################
-define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -cells {.*}
+define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro \
+  -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -cells {.*}
 add_pdn_connect -grid {CORE_macro_grid_2} -layers {M4 M5}

flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl

@@ -1,3 +1,5 @@
+# tclint-disable line-length
+
 set current_folder [file dirname [file normalize [info script]]]
 # Technology lib
 

flow/platforms/asap7/openlane/config.tcl

@@ -1,3 +1,5 @@
+# tclint-disable line-length
+
 # Process node
 set ::env(PROCESS) 7
 set ::env(DEF_UNITS_PER_MICRON) 1000

flow/platforms/ihp-sg13g2/pdn.tcl

@@ -19,10 +19,14 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
 # standard cell grid
 ####################################
 define_pdn_grid -name {grid} -voltage_domains {CORE}
-add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {5.0} -spacings {2.0} -core_offsets {4.5} -connect_to_pads
-add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring
-add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} -extend_to_core_ring
-add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} -extend_to_core_ring
+add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {5.0} -spacings {2.0} \
+  -core_offsets {4.5} -connect_to_pads
+add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins \
+  -extend_to_core_ring
+add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} \
+  -extend_to_core_ring
+add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} \
+  -extend_to_core_ring
 add_pdn_connect -grid {grid} -layers {Metal1 Metal5}
 add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1}
 # I/O pads

flow/platforms/nangate45/fakeram.tcl

@@ -31,8 +31,10 @@ proc copy_fakeram_results { } {
 
   foreach {design sizes} $design_rams {
     foreach size $sizes {
-      file copy -force $results_dir/fakeram45_$size/fakeram45_$size.lib $flow_dir/lib/fakeram45_$size.lib
-      file copy -force $results_dir/fakeram45_$size/fakeram45_$size.lef $flow_dir/lef/fakeram45_$size.lef
+      file copy -force \
+        $results_dir/fakeram45_$size/fakeram45_$size.lib $flow_dir/lib/fakeram45_$size.lib
+      file copy -force \
+        $results_dir/fakeram45_$size/fakeram45_$size.lef $flow_dir/lef/fakeram45_$size.lef
     }
   }
 }