Effect of SYNTH_NO_FLAT

[hmzsaeed]

What does the SYNTH_NO_FLAT actually do to a design? When I'm enabling it, the number of standard cells shows a drastic increase and so does the area. For example here, when I set SYNTH_NO_FLAT {1} , the number of standard cells increases from 585 to 305463.

[maliberty]

That is very extreme. Generally hierarchical will have somewhat worse results (as seen in rtl#1) but rtl#2 seems crazy. Is there some huge amount of logic that can be removed by optimization in the flat case? Are you certain your results are correct?

[hmzsaeed]

Yes, look at the log stats here:
with SYNTH_NO_FLAT {0} :

24. Printing statistics.

=== Generator ===

   Number of wires:                586
   Number of wire bits:            595
   Number of public wires:         140
   Number of public wire bits:     149
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                585
     sky130_fd_sc_hd__a211oi_2       2
     sky130_fd_sc_hd__a21bo_2        2
     sky130_fd_sc_hd__a21boi_2       2
     sky130_fd_sc_hd__a21o_2         6
     sky130_fd_sc_hd__a21oi_2       30
     sky130_fd_sc_hd__a22o_2         3
     sky130_fd_sc_hd__a31o_2        23
     sky130_fd_sc_hd__a32o_2         4
     sky130_fd_sc_hd__and2_2        40
     sky130_fd_sc_hd__and2b_2        3
     sky130_fd_sc_hd__and3_2        38
     sky130_fd_sc_hd__and3b_2       16
     sky130_fd_sc_hd__and4_2        23
     sky130_fd_sc_hd__buf_1         60
     sky130_fd_sc_hd__conb_1        12
     sky130_fd_sc_hd__dfxtp_2      120
     sky130_fd_sc_hd__inv_2         12
     sky130_fd_sc_hd__mux2_2         1
     sky130_fd_sc_hd__nand2_2       16
     sky130_fd_sc_hd__nand3_2        4
     sky130_fd_sc_hd__nand4_2        3
     sky130_fd_sc_hd__nor2_2        35
     sky130_fd_sc_hd__nor3_2         9
     sky130_fd_sc_hd__nor4_2         2
     sky130_fd_sc_hd__o211a_2        5
     sky130_fd_sc_hd__o21a_2        18
     sky130_fd_sc_hd__o21ai_2       35
     sky130_fd_sc_hd__o21ba_2        2
     sky130_fd_sc_hd__o2bb2a_2       1
     sky130_fd_sc_hd__o311a_2        2
     sky130_fd_sc_hd__o31a_2         3
     sky130_fd_sc_hd__o31ai_2        2
     sky130_fd_sc_hd__o41a_2         1
     sky130_fd_sc_hd__or2_2          9
     sky130_fd_sc_hd__or2b_2         1
     sky130_fd_sc_hd__or3_2          7
     sky130_fd_sc_hd__or3b_2         4
     sky130_fd_sc_hd__or4_2         23
     sky130_fd_sc_hd__or4b_2         2
     sky130_fd_sc_hd__xnor2_2        1
     sky130_fd_sc_hd__xor2_2         3
     
   Chip area for module '\Generator': 6127.126400

with SYNTH_NO_FLAT {1} :

36. Printing statistics.

=== Generator ===

Number of wires:             305464
Number of wire bits:         305473
Number of public wires:      305464
Number of public wire bits:  305473
Number of memories:               0
Number of memory bits:            0
Number of processes:              0
Number of cells:             305463
  sky130_fd_sc_hd__a2111o_2      22
  sky130_fd_sc_hd__a2111oi_2      2
  sky130_fd_sc_hd__a211o_2      489
  sky130_fd_sc_hd__a211oi_2     271
  sky130_fd_sc_hd__a21bo_2       88
  sky130_fd_sc_hd__a21boi_2      26
  sky130_fd_sc_hd__a21o_2      6595
  sky130_fd_sc_hd__a21oi_2     1885
  sky130_fd_sc_hd__a221o_2     3094
  sky130_fd_sc_hd__a221oi_2      16
  sky130_fd_sc_hd__a22o_2       259
  sky130_fd_sc_hd__a22oi_2      177
  sky130_fd_sc_hd__a2bb2o_2      49
  sky130_fd_sc_hd__a311o_2     1568
  sky130_fd_sc_hd__a311oi_2     135
  sky130_fd_sc_hd__a31o_2      1244
  sky130_fd_sc_hd__a31oi_2       91
  sky130_fd_sc_hd__a32o_2       206
  sky130_fd_sc_hd__a32oi_2        1
  sky130_fd_sc_hd__a41o_2        18
  sky130_fd_sc_hd__a41oi_2        1
  sky130_fd_sc_hd__and2_2      3334
  sky130_fd_sc_hd__and2b_2      789
  sky130_fd_sc_hd__and3_2      4564
  sky130_fd_sc_hd__and3b_2       74
  sky130_fd_sc_hd__and4_2       231
  sky130_fd_sc_hd__and4b_2       17
  sky130_fd_sc_hd__and4bb_2      49
  sky130_fd_sc_hd__buf_1      93989
  sky130_fd_sc_hd__buf_2       1809
  sky130_fd_sc_hd__conb_1       123
  sky130_fd_sc_hd__dfxtp_2    68877
  sky130_fd_sc_hd__inv_2        396
  sky130_fd_sc_hd__mux2_2     79489
  sky130_fd_sc_hd__mux4_2      9513
  sky130_fd_sc_hd__nand2_2     2686
  sky130_fd_sc_hd__nand2b_2      13
  sky130_fd_sc_hd__nand3_2      155
  sky130_fd_sc_hd__nand3b_2      64
  sky130_fd_sc_hd__nand4_2       26
  sky130_fd_sc_hd__nand4b_2       1
  sky130_fd_sc_hd__nor2_2      1820
  sky130_fd_sc_hd__nor2b_2       15
  sky130_fd_sc_hd__nor3_2        76
  sky130_fd_sc_hd__nor3b_2       11
  sky130_fd_sc_hd__nor4_2        17
  sky130_fd_sc_hd__nor4b_2        7
  sky130_fd_sc_hd__o2111a_2       9
  sky130_fd_sc_hd__o2111ai_2      2
  sky130_fd_sc_hd__o211a_2     2392
  sky130_fd_sc_hd__o211ai_2     570
  sky130_fd_sc_hd__o21a_2      4617
  sky130_fd_sc_hd__o21ai_2     1534
  sky130_fd_sc_hd__o21ba_2     1155
  sky130_fd_sc_hd__o21bai_2      44
  sky130_fd_sc_hd__o221a_2     2204
  sky130_fd_sc_hd__o221ai_2      51
  sky130_fd_sc_hd__o22a_2       114
  sky130_fd_sc_hd__o22ai_2        9
  sky130_fd_sc_hd__o2bb2a_2      96
  sky130_fd_sc_hd__o311a_2     1071
  sky130_fd_sc_hd__o311ai_2      82
  sky130_fd_sc_hd__o31a_2       365
  sky130_fd_sc_hd__o31ai_2       49
  sky130_fd_sc_hd__o32a_2       204
  sky130_fd_sc_hd__o41a_2         4
  sky130_fd_sc_hd__o41ai_2        1
  sky130_fd_sc_hd__or2_2       3319
  sky130_fd_sc_hd__or2b_2      2050
  sky130_fd_sc_hd__or3_2        257
  sky130_fd_sc_hd__or3b_2       155
  sky130_fd_sc_hd__or4_2        169
  sky130_fd_sc_hd__or4b_2        32
  sky130_fd_sc_hd__or4bb_2       13
  sky130_fd_sc_hd__xnor2_2      390
  sky130_fd_sc_hd__xor2_2       123

Chip area for module '\Generator': 3396672.678390

[maliberty]

Can you provide a test case?

[hmzsaeed]

Generator.zip

[maliberty]

It is a bit incomplete as a test case as you didn't provide any script to run in yosys. I made one up and I see the general trend you describe.

I also see a lot of constants being passed through the hierarchy in your netlist. Those case can't be optimized when running hierarchical synthesis. In the flat case they can. I suspect you have effectively disabled almost all the logic in your design this way and so yosys optimizes it away. Its a bit hard to tell in a large generated .v file - is that your intent?

[maliberty]

Also in flat:

3.3. Executing FLATTEN pass (flatten design).
Deleting now unused module Switch1toN.
Deleting now unused module Core.
Deleting now unused module PC.
Deleting now unused module MemoryFetch.
Deleting now unused module Execute.
Deleting now unused module MduControl.
Deleting now unused module MDU.
Deleting now unused module ForwardingUnit.
Deleting now unused module AluControl.
Deleting now unused module ALU.
Deleting now unused module InstructionDecode.
Deleting now unused module BranchUnit.
Deleting now unused module ImmediateGen.
Deleting now unused module Registers.
Deleting now unused module Control.
Deleting now unused module HazardUnit.
Deleting now unused module InstructionFetch.
Deleting now unused module WishboneErr.
Deleting now unused module BlockRamWithMasking.
Deleting now unused module BlockRamWithoutMasking.
Deleting now unused module i2c.
Deleting now unused module I2C_Top.
Deleting now unused module i2c_master.
Deleting now unused module SpiFlash.
Deleting now unused module Timer.
Deleting now unused module uart.
Deleting now unused module UartTOP.
Deleting now unused module uartRX.
Deleting now unused module uartTX.
Deleting now unused module Spi.
Deleting now unused module Protocol.
Deleting now unused module Gpio.
Deleting now unused module IntrHardware.
Deleting now unused module GpioRegTop.
Deleting now unused module SubRegExt_2.
Deleting now unused module SubReg_2.
Deleting now unused module SubRegExt.
Deleting now unused module SubReg_1.
Deleting now unused module SubReg.
Deleting now unused module WishboneDevice.
Deleting now unused module WishboneHost.

[hmzsaeed]

Thanks Matt. The issue is in RTL of the design. I thought this flag was doing something else, thanks for clearing that up.