how to work with multiple verilog files

[IngYordiDelgado]

i tried to test a project with multiple verilog files, i put this files on a directory called rtl in the configuration file i set the verilog file to the path of my top level file and its name and im getting the following error
[ERROR]: during executing: "yosys -c /openlane/scripts/yosys/synth.tcl -l /openlane/designs/gcd/runs/RUN_2022.09.10_00.07.58/logs/synthesis/1-synthesis.log |& tee /dev/null"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:

2. Generating Graphviz representation of design.
   Writing dot description to `/openlane/designs/gcd/runs/RUN_2022.09.10_00.07.58/tmp/synthesis/hierarchy.dot'.
   Dumping module gcd to page 1.

3. Executing HIERARCHY pass (managing design hierarchy).

3.1. Analyzing design hierarchy..
ERROR: Module \gcd_control' referenced in module \gcd' in cell `\GCDctrl0' is not part of the design.
child process exited abnormally

[vijayank88]

GCDctrl0 module missing the file list. Use correct path in config.tcl

[IngYordiDelgado]

how to set multiple verilog files ? my config file is like this
{
"DESIGN_NAME": "gcd",
"VERILOG_FILES": "dir::rtl/src/gcd.v",
"CLOCK_PORT": "clk",
how can i add more files to the list ?

[vijayank88]

If it's single directory use following: dir::rtl/src/*.v

Refer the document link: https://openlane.readthedocs.io/en/latest/usage/designs.html#adding-your-designs
If you're good in tcl, use following format: https://github.com/The-OpenROAD-Project/OpenLane/blob/master/designs/caravel_upw/config.tcl