[BUG] Trailing whitespaces in generated RTL

[lizhiliTT]

Hello Alex,

I found four more instances when the generated RTL has trailing whitespace. May you fix it? Thanks!

Case 1: First register of address map is writable external register

// ...
    } field_storage_t;
    field_storage_t field_storage;

    // <- HERE
    assign hwif_out.WRITABLE_EXT_REG.req = decoded_req_is_wr ? decoded_reg_strb.FIELD : '0;
    assign hwif_out.WRITABLE_EXT_REG.req_is_wr = decoded_req_is_wr;
    assign hwif_out.WRITABLE_EXT_REG.wr_data = decoded_wr_data;
    assign hwif_out.WRITABLE_EXT_REG.wr_biten = decoded_wr_biten;
// ...

Case 2: No field_combo and/or no field storage

// ...
    //--------------------------------------------------------------------------
    // Field logic
    //--------------------------------------------------------------------------
    // <- HERE

    // <- HERE
// ...

Case 3: Address map with read-only or write-only external registers only

// ...
    //--------------------------------------------------------------------------
    // Readback
    //--------------------------------------------------------------------------
    logic readback_external_rd_ack_c;
    always_comb begin
        automatic logic rd_ack;
        rd_ack = '0;
        // <- HERE
        readback_external_rd_ack_c = rd_ack;
    end
// ...

// ...
    //--------------------------------------------------------------------------
    // Write response
    //--------------------------------------------------------------------------
    always_comb begin
        automatic logic wr_ack;
        wr_ack = '0;
        // <- HERE
        external_wr_ack = wr_ack;
    end
// ...

Case 4: Interrupt register

//...
    always_comb begin
        automatic logic [0:0] next_c;
        automatic logic load_next_c;
        next_c = field_storage.INTR_REG.FIELD.value;
        load_next_c = '0;
        // <- HERE
        // HW Write
// ...

Regards,
Leo