Merge branch 'YosysHQ:main' into main

Author: akashlevy

frontends/verilog/verilog_parser.y

@@ -3289,15 +3289,19 @@ basic_expr:
 		$$ = AstNode::mkconst_str(@1, *$1);
 		SET_AST_NODE_LOC($$.get(), @1, @1);
 	} |
-	hierarchical_id attr {
-		// super sketchy! Orphaned pointer in non-owning extra->ast_stack
-		AstNode *node = new AstNode(@1, AST_FCALL);
-		node->str = *$1;
-		extra->ast_stack.push_back(node);
-		SET_AST_NODE_LOC(node, @1, @1);
-		append_attr(node, std::move($2));
+	hierarchical_id attr <ast_t>{
+		// Here we use "Typed Midrule Actions".
+		// https://www.gnu.org/software/bison/manual/html_node/Typed-Midrule-Actions.html
+		auto fcall = std::make_unique<AstNode>(@1, AST_FCALL);
+		AstNode *fcall_node = fcall.get();
+		fcall_node->str = *$1;
+		extra->ast_stack.push_back(fcall_node);
+		SET_AST_NODE_LOC(fcall_node, @1, @1);
+		append_attr(fcall_node, std::move($2));
+		$$ = std::move(fcall);
 	} TOK_LPAREN arg_list optional_comma TOK_RPAREN {
-		$$.reset(extra->ast_stack.back());
+		log_assert($3 != nullptr);
+		$$ = std::move($3);
 		extra->ast_stack.pop_back();
 	} |
 	TOK_TO_SIGNED attr TOK_LPAREN expr TOK_RPAREN {

passes/cmds/show.cc

@@ -59,6 +59,7 @@ struct ShowWorker
 	RTLIL::Module *module;
 	uint32_t currentColor;
 	bool genWidthLabels;
+	std::string wireshape;
 	bool genSignedLabels;
 	bool stretchIO;
 	bool enumerateIds;
@@ -428,16 +429,19 @@ struct ShowWorker
 
 		std::map<std::string, std::string> wires_on_demand;
 		for (auto wire : module->selected_wires()) {
-			const char *shape = "diamond";
+		    std::string shape = wireshape;
 			if (wire->port_input || wire->port_output)
 				shape = "octagon";
+			const bool is_borderless = (shape == "plaintext") || (shape == "plain") || (shape == "none");
 			if (wire->name.isPublic()) {
 				std::string src_href;
 				if (href && wire->attributes.count(ID::src) > 0)
 					src_href = stringf(", href=\"%s\" ", escape(wire->attributes.at(ID::src).decode_string()));
-				fprintf(f, "n%d [ shape=%s, label=\"%s\", %s%s];\n",
-						id2num(wire->name), shape, findLabel(wire->name.str()),
-						nextColor(RTLIL::SigSpec(wire), "color=\"black\", fontcolor=\"black\"").c_str(),
+				fprintf(f, "n%d [ shape=%s,%s label=\"%s\", %s%s];\n",
+						id2num(wire->name), shape.c_str(), is_borderless? " margin=0, width=0" : "",  findLabel(wire->name.str()),
+						is_borderless
+						    ? "color=\"none\", fontcolor=\"black\""
+							: nextColor(RTLIL::SigSpec(wire), "color=\"black\", fontcolor=\"black\"").c_str(), 
 						src_href.c_str());
 				if (wire->port_input)
 					all_sources.insert(stringf("n%d", id2num(wire->name)));
@@ -616,10 +620,10 @@ struct ShowWorker
 	}
 
 	ShowWorker(FILE *f, RTLIL::Design *design, std::vector<RTLIL::Design*> &libs, uint32_t colorSeed, bool genWidthLabels,
-			bool genSignedLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle, bool href,
+			const std::string wireshape, bool genSignedLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle, bool href,
 			const std::vector<std::pair<std::string, RTLIL::Selection>> &color_selections,
 			const std::vector<std::pair<std::string, RTLIL::Selection>> &label_selections, RTLIL::IdString colorattr) :
-			f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels),
+			f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels), wireshape(wireshape),
 			genSignedLabels(genSignedLabels), stretchIO(stretchIO), enumerateIds(enumerateIds), abbreviateIds(abbreviateIds),
 			notitle(notitle), href(href), color_selections(color_selections), label_selections(label_selections), colorattr(colorattr)
 	{
@@ -712,6 +716,9 @@ struct ShowPass : public Pass {
 		log("        Use the specified attribute to assign colors. A unique color is\n");
 		log("        assigned to each unique value of this attribute.\n");
 		log("\n");
+		log("    -wireshape <graphviz_shape>\n");
+		log("        Use the specified shape for wire nodes. E.g. plaintext.\n");
+		log("\n");
 		log("    -width\n");
 		log("        annotate buses with a label indicating the width of the bus.\n");
 		log("\n");
@@ -770,6 +777,7 @@ struct ShowPass : public Pass {
 		std::string prefix = stringf("%s/.yosys_show", getenv("HOME") ? getenv("HOME") : ".");
 #endif
 		std::string viewer_exe;
+		std::string flag_wireshape = "diamond";
 		std::vector<std::string> libfiles;
 		std::vector<RTLIL::Design*> libs;
 		uint32_t colorSeed = 0;
@@ -834,6 +842,10 @@ struct ShowPass : public Pass {
 				format = args[++argidx];
 				continue;
 			}
+			if (arg == "-wireshape" && argidx+1 < args.size()) {
+				flag_wireshape = args[++argidx];
+				continue;
+			}
 			if (arg == "-width") {
 				flag_width= true;
 				continue;
@@ -916,7 +928,7 @@ struct ShowPass : public Pass {
 				delete lib;
 			log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str());
 		}
-		ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, flag_href, color_selections, label_selections, colorattr);
+		ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_wireshape, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, flag_href, color_selections, label_selections, colorattr);
 		fclose(f);
 
 		for (auto lib : libs)

tests/cxxrtl/run-test.sh

@@ -5,7 +5,7 @@ set -ex
 run_subtest () {
     local subtest=$1; shift
 
-    ${CC:-gcc} -std=c++11 -O2 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++
+    ${CXX:-g++} -std=c++11 -O2 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++
     ./cxxrtl-test-${subtest}
 }
 
@@ -14,4 +14,4 @@ run_subtest value_fuzz
 
 # Compile-only test.
 ../../yosys -p "read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc"
-${CC:-gcc} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc
+${CXX:-g++} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc

tests/fmt/run-test.sh

@@ -51,7 +51,7 @@ test_cxxrtl () {
 	local subtest=$1; shift
 
 	../../yosys -p "read_verilog ${subtest}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-${subtest}.cc"
-	${CC:-gcc} -std=c++11 -o yosys-${subtest} -I../../backends/cxxrtl/runtime ${subtest}_tb.cc -lstdc++
+	${CXX:-g++} -std=c++11 -o yosys-${subtest} -I../../backends/cxxrtl/runtime ${subtest}_tb.cc -lstdc++
 	./yosys-${subtest} 2>yosys-${subtest}.log
 	iverilog -o iverilog-${subtest} ${subtest}.v ${subtest}_tb.v
 	./iverilog-${subtest} |grep -v '\$finish called' >iverilog-${subtest}.log
@@ -69,7 +69,7 @@ diff iverilog-always_full.log iverilog-always_full-1.log
 
 ../../yosys -p "read_verilog display_lm.v" >yosys-display_lm.log
 ../../yosys -p "read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc"
-${CC:-gcc} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++
+${CXX:-g++} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++
 ./yosys-display_lm_cc >yosys-display_lm_cc.log
 for log in yosys-display_lm.log yosys-display_lm_cc.log; do
 	grep "^%l: \\\\bot\$" "$log"

tests/tools/autotest.sh

@@ -26,7 +26,7 @@ xfirrtl="../xfirrtl"
 abcprog="$toolsdir/../../yosys-abc"
 
 if [ ! -f "$toolsdir/cmp_tbdata" -o "$toolsdir/cmp_tbdata.c" -nt "$toolsdir/cmp_tbdata" ]; then
-	( set -ex; ${CC:-gcc} -Wall -o "$toolsdir/cmp_tbdata" "$toolsdir/cmp_tbdata.c"; ) || exit 1
+	( set -ex; ${CXX:-g++} -Wall -o "$toolsdir/cmp_tbdata" "$toolsdir/cmp_tbdata.c"; ) || exit 1
 fi
 
 while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do