Zilog DMA knowledge gap

[ped7g]

Going by Zilog DMA manual, the BB command setting read mask says:

When the read mask has been programmed, it must be initialized to begin at
the lowest-order register selected. Do this with the INITIATE READ
SEQUENCE command.

But the A7 Initiate Read Sequence says:

When started, the read
sequence specified by the read mask must be completed before, for
example, giving another INITIATE READ SEQUENCE or a READ
STATUS BYTE command.

Registers do not need to be read immediately after writing the INITIATE
READ SEQUENCE command. Other commands (except INITIATE READ
SEQUENCE and READ STATUS BYTE) can be written and can go through
bus-request/bus release cycles before executing the first read and subse-
quent reads.

Also the read mask is 0x7F after power-on, so A7 should lead to reading full set.

Knowledge gap - to be tested with real HW (both ZX Next and Zilog DMA):

• I guess the following points are worth full new test, so the test can be easily run by anyone owning the HW, not requiring precise inputs into interactive DMA test. So add single screen test showing various read scenarios.
• (zilog) I think I did test that reading DMA port without BF (read status byte) or A7 (Init read sequence) returns bogus values, somewhat similar to status, but not really status byte (or maybe it was reading full sequence in cycle, but I think the weird almost-status value was stable, ie. doesn't match the 0x7F default mask) -> to be verified one more time, that Zilog DMA doesn't put anything meaningful on the read port without commanding it first.
• (zilog) verify that A7 and BF are truly ignored when some bytes to read are still pending
• (next) verify that A7 and BF both override the reading status even when bytes to read are still pending (VHDL reading, needs confirmation)
• (zilog) does the BB cause implicit A7, ie. you can just read the port after BB? The docs sounds like NOT, the A7 is required.
• (next) the BB does cause implicit A7 (based on VHDL reading) -> confirm
• (zilog) if there was partially read A7 sequence, then BB is sent with different mask, then A7 is sent, is the A7 skipped because first sequence was not read fully, or BB does cancel current sequence and second A7 will initialize read sequence?
• (zilog) BF read status byte halfway into read-sequence - is it ignored or resets the reading to status byte?
• (next) confirm BF is forced and works also halfway into read sequence
• (zilog vs next) other peculiarities to confirm: LOAD reset counter only on zilog, counter/source/destination address values after transfer (next in both zilog/zxn modes vs real zilog) to make it 100% clear where +1/same/-1 logic is applied to original transfer values
• document this inner working and real results in tests code/readme, so nobody has to ever touch this again if they are curious, and can just read the info

edit with more info about zxnDMA:

VHDL:
https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/-/blob/master/cores/zxnext/src/device/dma.vhd?ref_type=heads#L730
https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/-/blob/master/cores/zxnext/src/device/dma.vhd?ref_type=heads#L859
vs
https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/-/blob/master/cores/zxnext/src/device/dma.vhd?ref_type=heads#L694
without any deep understanding of VHDL, this looks to me like implicit A7 happening, the reg_rd_seq_s is set after BB + mask byte too.
AND the A7 works also mid-way into the read sequence, so that's probably another difference from Zilog DMA (if even Zilog works as docs say, maybe it does not)