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fibonacci updated on viz
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6 files changed

+5072
-329
lines changed

6 files changed

+5072
-329
lines changed

‎pipelined/testcases/11.s‎

Lines changed: 14 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,22 +1,23 @@
11
start:
2-
addi x10, x0, 10 # Load n
3-
addi x11, x0, 0 # x11 = 0 (Fib(0))
4-
addi x12, x0, 1 # x12 = 1 (Fib(1))
5-
beq x10, x0, done # If n == 0, return Fib(0)
6-
addi x10, x10, -1 # Decrement n by 1 to account for Fib(1)
7-
beq x10, x0, done1 # If n == 1, return Fib(1)
2+
addi x1, x0, 10 # Load n
3+
addi x2, x0, 0 # x2 = 0 (Fib(0))
4+
addi x3, x0, 1 # x3 = 1 (Fib(1))
5+
beq x1, x0, done # If n == 0, return Fib(0)
6+
addi x1, x1, -1 # Decrement n by 1 to account for Fib(1)
7+
beq x1, x0, done1 # If n == 1, return Fib(1)
88

99
loop:
10-
add x13, x11, x12 # x13 = x11 + x12 (Fib(n) = Fib(n-1) + Fib(n-2))
11-
add x11, x12, x0 # x11 = x12 (shift Fib(n-1) to Fib(n-2))
12-
add x12, x13, x0 # x12 = x13 (shift Fib(n) to Fib(n-1))
13-
addi x10, x10, -1 # Decrement n
14-
beq x10, x0, done1 # Repeat until n == 0
10+
add x4, x2, x3 # x4 = x2 + x3 (Fib(n) = Fib(n-1) + Fib(n-2))
11+
add x2, x3, x0 # x2 = x3 (shift Fib(n-1) to Fib(n-2))
12+
add x3, x4, x0 # x3 = x4 (shift Fib(n) to Fib(n-1))
13+
addi x1, x1, -1 # Decrement n
14+
beq x1, x0, done1 # Repeat until n == 0
1515
beq x0, x0, loop
1616

1717
done1:
18-
add x13, x12, x0 # Return Fib(1)
18+
add x4, x3, x0 # Return Fib(1)
1919

2020
done:
21-
# x13 holds the Fibonacci result
21+
# x4 holds the Fibonacci result
22+
addi x0 x0 0
2223
nop

‎pipelined/testcases/assembler.py‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -361,7 +361,11 @@ def generate_testbench(instructions):
361361
$display("MEM/WB: Instruction=%h, rd=x%0d, RegWrite=%b, MemToReg=%b",
362362
cpu.mem_wb_instruction, cpu.mem_wb_rd, cpu.mem_wb_reg_write,
363363
cpu.mem_wb_mem_to_reg);
364-
364+
$display("Register Values:");
365+
for (i = 0; i < 32; i = i + 1) begin
366+
$display("reg[%0d]=%0d", i, cpu.reg_file.registers[i]);
367+
end
368+
365369
// Hazard detection information
366370
if (cpu.stall) begin // Use cpu.stall directly instead of cpu.hazard_detection_unit.stall_pipeline
367371
$display("HAZARD DETECTED: Stalling pipeline");

‎pipelined/verilog/testbench_pipelined.v‎

Lines changed: 19 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -16,13 +16,21 @@ module testbench_pipelined();
1616
reset = 1;
1717

1818
// Initialize instruction memory first
19-
cpu.imem.memory[0] = 32'b00000000001100000000000010010011;
20-
cpu.imem.memory[1] = 32'b00000000011100000000000100010011;
21-
cpu.imem.memory[2] = 32'b00000000000000001000100001100011;
22-
cpu.imem.memory[3] = 32'b00000000000100010000000100110011;
19+
cpu.imem.memory[0] = 32'b00000000101000000000000010010011;
20+
cpu.imem.memory[1] = 32'b00000000000000000000000100010011;
21+
cpu.imem.memory[2] = 32'b00000000000100000000000110010011;
22+
cpu.imem.memory[3] = 32'b00000010000000001000010001100011;
2323
cpu.imem.memory[4] = 32'b11111111111100001000000010010011;
24-
cpu.imem.memory[5] = 32'b11111110000000000000101011100011;
25-
cpu.imem.memory[6] = 32'b00000000000000000000000000000000;
24+
cpu.imem.memory[5] = 32'b00000000000000001000111001100011;
25+
cpu.imem.memory[6] = 32'b00000000001100010000001000110011;
26+
cpu.imem.memory[7] = 32'b00000000000000011000000100110011;
27+
cpu.imem.memory[8] = 32'b00000000000000100000000110110011;
28+
cpu.imem.memory[9] = 32'b11111111111100001000000010010011;
29+
cpu.imem.memory[10] = 32'b00000000000000001000010001100011;
30+
cpu.imem.memory[11] = 32'b11111110000000000000011011100011;
31+
cpu.imem.memory[12] = 32'b00000000000000011000001000110011;
32+
cpu.imem.memory[13] = 32'b00000000000000000000000000010011;
33+
cpu.imem.memory[14] = 32'b00000000000000000000000000000000;
2634

2735
// promper initialization
2836
#10 reset = 0;
@@ -157,7 +165,11 @@ module testbench_pipelined();
157165
$display("MEM/WB: Instruction=%h, rd=x%0d, RegWrite=%b, MemToReg=%b",
158166
cpu.mem_wb_instruction, cpu.mem_wb_rd, cpu.mem_wb_reg_write,
159167
cpu.mem_wb_mem_to_reg);
160-
168+
$display("Register Values:");
169+
for (i = 0; i < 32; i = i + 1) begin
170+
$display("reg[%0d]=%0d", i, cpu.reg_file.registers[i]);
171+
end
172+
161173
// Hazard detection information
162174
if (cpu.stall) begin // Use cpu.stall directly instead of cpu.hazard_detection_unit.stall_pipeline
163175
$display("HAZARD DETECTED: Stalling pipeline");

‎pipelined/visualization/parse-pipeline.py‎

Lines changed: 30 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,9 @@ def parse_pipeline_output(file_path):
99
cycles = []
1010
cycle_blocks = content.split("--------------------------------")
1111

12+
current_registers = {f"x{i}": 0 for i in range(32)}
13+
current_memory = {}
14+
1215
# Parse the cycle-by-cycle data
1316
for block in cycle_blocks:
1417
if "Time=" not in block:
@@ -21,6 +24,8 @@ def parse_pipeline_output(file_path):
2124
if cycle_match:
2225
cycle_data["cycle"] = int(cycle_match.group(1))
2326

27+
# Clear the changed registers from previous cycle
28+
changed_registers = set()
2429
# Extract IF stage data
2530
pc_match = re.search(r"IF Stage: PC=([0-9a-fA-Fx]+)", block)
2631
if pc_match:
@@ -85,12 +90,35 @@ def parse_pipeline_output(file_path):
8590
cycle_data["mem_write"] = bool(int(control_match.group(4)))
8691
cycle_data["alu_src"] = bool(int(control_match.group(5)))
8792
cycle_data["reg_write"] = bool(int(control_match.group(6)))
93+
94+
reg_values = {}
95+
reg_matches = re.findall(r"reg\[(\d+)\]=(-?\d+)", block)
96+
for reg_match in reg_matches:
97+
reg_num = int(reg_match[0])
98+
reg_value = int(reg_match[1])
99+
reg_name = f"x{reg_num}"
100+
reg_values[reg_name] = reg_value
101+
102+
# Update our register tracking
103+
if current_registers.get(reg_name, 0) != reg_value:
104+
cycle_data[f"{reg_name}_changed"] = True
105+
current_registers[reg_name] = reg_value
106+
107+
# Copy all current register values to this cycle
108+
for reg, value in current_registers.items():
109+
cycle_data[reg] = value
110+
111+
# Mark which registers changed this cycle
112+
for reg_name in changed_registers:
113+
cycle_data[f"{reg_name}_changed"] = True
88114

89115
# Extract WB activity (register writes)
90116
wb_match = re.search(r"WB Stage: Writing (-?\d+) to register x(\d+)", block)
91117
if wb_match:
92118
cycle_data["reg_write_data"] = int(wb_match.group(1))
93119
cycle_data["reg_write_rd"] = int(wb_match.group(2))
120+
reg_name = f"x{int(wb_match.group(2))}"
121+
cycle_data[f"{reg_name}_written"] = True
94122

95123
# Extract memory access information
96124
mem_read_match = re.search(r"MEM Stage: Reading from address (-?\d+), value=(-?\d+)", block)
@@ -108,7 +136,6 @@ def parse_pipeline_output(file_path):
108136
cycle_data["if_stalled"] = True
109137
cycle_data["id_stalled"] = True
110138

111-
# Check for load-use hazard keywords
112139
if "hazard detected" in block.lower() or "stalling pipeline" in block.lower():
113140
cycle_data["stall"] = True
114141
cycle_data["load_hazard"] = True
@@ -188,10 +215,9 @@ def parse_pipeline_output(file_path):
188215
cycle_data["flush_occurred"] = True
189216
cycle_data["pipeline_recovery"] = True
190217

191-
192218
cycles.append(cycle_data)
193219

194-
# Parse final register and memory state
220+
# Process final memory and register state
195221
final_registers = {}
196222
final_memory = {}
197223

@@ -215,7 +241,7 @@ def parse_pipeline_output(file_path):
215241
mem_value = int(match[1])
216242
final_memory[f"mem_{mem_addr}"] = mem_value
217243

218-
# Add the final register and memory values to the last cycle
244+
# Ensure we have all register values in the last cycle
219245
if cycles and final_registers:
220246
for reg_name, reg_value in final_registers.items():
221247
cycles[-1][reg_name] = reg_value

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