fix:Registers updates fetching

Author: MostlyKIGuess

demo/pipelined/pipeline-data.js

@@ -704,7 +704,71 @@ const pipelineData = {
       "mem_to_reg": false,
       "mem_write": false,
       "alu_src": false,
-      "reg_write": false
+      "reg_write": false,
+      "x0": 0,
+      "x1": 0,
+      "x2": 13,
+      "x3": 0,
+      "x4": 0,
+      "x5": 0,
+      "x6": 0,
+      "x7": 0,
+      "x8": 0,
+      "x9": 0,
+      "x10": 0,
+      "x11": 0,
+      "x12": 0,
+      "x13": 0,
+      "x14": 0,
+      "x15": 0,
+      "x16": 0,
+      "x17": 0,
+      "x18": 0,
+      "x19": 0,
+      "x20": 0,
+      "x21": 0,
+      "x22": 0,
+      "x23": 0,
+      "x24": 0,
+      "x25": 0,
+      "x26": 0,
+      "x27": 0,
+      "x28": 0,
+      "x29": 0,
+      "x30": 0,
+      "x31": 0,
+      "mem_0": 5,
+      "mem_1": 0,
+      "mem_2": 0,
+      "mem_3": 0,
+      "mem_4": 0,
+      "mem_5": 0,
+      "mem_6": 0,
+      "mem_7": 0,
+      "mem_8": 0,
+      "mem_9": 0,
+      "mem_10": 0,
+      "mem_11": 0,
+      "mem_12": 0,
+      "mem_13": 0,
+      "mem_14": 0,
+      "mem_15": 0,
+      "mem_16": 0,
+      "mem_17": 0,
+      "mem_18": 0,
+      "mem_19": 0,
+      "mem_20": 0,
+      "mem_21": 0,
+      "mem_22": 0,
+      "mem_23": 0,
+      "mem_24": 0,
+      "mem_25": 0,
+      "mem_26": 0,
+      "mem_27": 0,
+      "mem_28": 0,
+      "mem_29": 0,
+      "mem_30": 0,
+      "mem_31": 0
     }
   ]
-};
+};

pipelined/visualization/parse-pipeline.py

@@ -9,6 +9,7 @@ def parse_pipeline_output(file_path):
     cycles = []
     cycle_blocks = content.split("--------------------------------")
 
+    # Parse the cycle-by-cycle data
     for block in cycle_blocks:
         if "Time=" not in block:
             continue
@@ -187,10 +188,41 @@ def parse_pipeline_output(file_path):
             cycle_data["flush_occurred"] = True
             cycle_data["pipeline_recovery"] = True
 
-        
-        
+ 
         cycles.append(cycle_data)
 
+    # Parse final register and memory state
+    final_registers = {}
+    final_memory = {}
+    
+    # Extract final register values
+    reg_section = re.search(r"Register file contents:(.*?)Memory contents:", content, re.DOTALL)
+    if reg_section:
+        reg_content = reg_section.group(1)
+        reg_matches = re.findall(r"x(\d+) = (-?\d+)", reg_content)
+        for match in reg_matches:
+            reg_num = int(match[0])
+            reg_value = int(match[1])
+            final_registers[f"x{reg_num}"] = reg_value
+    
+    # Extract final memory values
+    mem_section = re.search(r"Memory contents:(.*?)Data memory contents written", content, re.DOTALL)
+    if mem_section:
+        mem_content = mem_section.group(1)
+        mem_matches = re.findall(r"mem\[(\d+)\] = (-?\d+)", mem_content)
+        for match in mem_matches:
+            mem_addr = int(match[0])
+            mem_value = int(match[1])
+            final_memory[f"mem_{mem_addr}"] = mem_value
+    
+    # Add the final register and memory values to the last cycle
+    if cycles and final_registers:
+        for reg_name, reg_value in final_registers.items():
+            cycles[-1][reg_name] = reg_value
+            
+    if cycles and final_memory:
+        for mem_name, mem_value in final_memory.items():
+            cycles[-1][mem_name] = mem_value
 
     return {"cycles": cycles}
 

pipelined/visualization/pipeline-data.js

@@ -704,7 +704,71 @@ const pipelineData = {
       "mem_to_reg": false,
       "mem_write": false,
       "alu_src": false,
-      "reg_write": false
+      "reg_write": false,
+      "x0": 0,
+      "x1": 0,
+      "x2": 13,
+      "x3": 0,
+      "x4": 0,
+      "x5": 0,
+      "x6": 0,
+      "x7": 0,
+      "x8": 0,
+      "x9": 0,
+      "x10": 0,
+      "x11": 0,
+      "x12": 0,
+      "x13": 0,
+      "x14": 0,
+      "x15": 0,
+      "x16": 0,
+      "x17": 0,
+      "x18": 0,
+      "x19": 0,
+      "x20": 0,
+      "x21": 0,
+      "x22": 0,
+      "x23": 0,
+      "x24": 0,
+      "x25": 0,
+      "x26": 0,
+      "x27": 0,
+      "x28": 0,
+      "x29": 0,
+      "x30": 0,
+      "x31": 0,
+      "mem_0": 5,
+      "mem_1": 0,
+      "mem_2": 0,
+      "mem_3": 0,
+      "mem_4": 0,
+      "mem_5": 0,
+      "mem_6": 0,
+      "mem_7": 0,
+      "mem_8": 0,
+      "mem_9": 0,
+      "mem_10": 0,
+      "mem_11": 0,
+      "mem_12": 0,
+      "mem_13": 0,
+      "mem_14": 0,
+      "mem_15": 0,
+      "mem_16": 0,
+      "mem_17": 0,
+      "mem_18": 0,
+      "mem_19": 0,
+      "mem_20": 0,
+      "mem_21": 0,
+      "mem_22": 0,
+      "mem_23": 0,
+      "mem_24": 0,
+      "mem_25": 0,
+      "mem_26": 0,
+      "mem_27": 0,
+      "mem_28": 0,
+      "mem_29": 0,
+      "mem_30": 0,
+      "mem_31": 0
     }
   ]
 };