1- From 00006a6046fa2604cfea07d4e971ae3e10c900da Mon Sep 17 00:00:00 2001
1+ From 0849d29f4645b73132a0b612aa92289469720dce Mon Sep 17 00:00:00 2001
22From: Vadim Pasternak <
[email protected] >
33Date: Thu, 4 Jan 2024 07:40:04 +0000
4- Subject: [PATCH 3/7 ] platform: mellanox: Downstream: Introduce support of
5- Nvidia next genration L1 tray switch
4+ Subject: [PATCH platform-next 3/8 ] platform: mellanox: Downstream: Introduce
5+ support of Nvidia next genration L1 tray switch
66
77Add support for new L1 tray switch node providing L1 connectivity for
88multi-node networking chassis.
@@ -17,11 +17,11 @@ of the all required platform driver.
1717Signed-off-by: Oleksandr Shamray <
[email protected] >
1818Reviewed-by: Vadim Pasternak <
[email protected] >
1919---
20- drivers/platform/mellanox/mlx-platform.c | 1143 ++++++++++++++++++++--
21- 1 file changed, 1043 insertions(+), 100 deletions(-)
20+ drivers/platform/mellanox/mlx-platform.c | 1155 ++++++++++++++++++++--
21+ 1 file changed, 1055 insertions(+), 100 deletions(-)
2222
2323diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c
24- index 4be0f29cc..3787dc8fb 100644
24+ index 4be0f29cc..a867ba4f8 100644
2525--- a/drivers/platform/mellanox/mlx-platform.c
2626+++ b/drivers/platform/mellanox/mlx-platform.c
2727@@ -53,6 +53,7 @@
@@ -246,7 +246,7 @@ index 4be0f29cc..3787dc8fb 100644
246246 {
247247 .label = "erot1_recovery",
248248 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
249- @@ -7012,139 +7151,693 @@ static struct mlxreg_core_platform_data mlxplat_smart_switch_regs_io_data = {
249+ @@ -7012,139 +7151,705 @@ static struct mlxreg_core_platform_data mlxplat_smart_switch_regs_io_data = {
250250 .counter = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_regs_io_data),
251251 };
252252
@@ -584,6 +584,18 @@ index 4be0f29cc..3787dc8fb 100644
584584+ .mode = 0444,
585585+ },
586586+ {
587+ + .label = "leakage5",
588+ + .reg = MLXPLAT_CPLD_LPC_REG_LEAK_OFFSET,
589+ + .mask = GENMASK(7, 0) & ~BIT(4),
590+ + .mode = 0444,
591+ + },
592+ + {
593+ + .label = "leakage6",
594+ + .reg = MLXPLAT_CPLD_LPC_REG_LEAK_OFFSET,
595+ + .mask = GENMASK(7, 0) & ~BIT(5),
596+ + .mode = 0444,
597+ + },
598+ + {
587599+ .label = "leakage_status_clear",
588600+ .reg = MLXPLAT_CPLD_LPC_REG_LEAK_EVENT_OFFSET,
589601+ .bit = GENMASK(5, 0),
@@ -722,7 +734,7 @@ index 4be0f29cc..3787dc8fb 100644
722734+ .mode = 0444,
723735+ },
724736+ {
725- + .label = "reset_main_5v ",
737+ + .label = "reset_main_51v ",
726738+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
727739+ .mask = GENMASK(7, 0) & ~BIT(6),
728740+ .mode = 0444,
@@ -1036,7 +1048,7 @@ index 4be0f29cc..3787dc8fb 100644
10361048 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET,
10371049 },
10381050 };
1039- @@ -7435,6 +8128 ,124 @@ static struct mlxreg_core_platform_data mlxplat_xdr_fan_data = {
1051+ @@ -7435,6 +8140 ,124 @@ static struct mlxreg_core_platform_data mlxplat_xdr_fan_data = {
10401052 .version = 1,
10411053 };
10421054
@@ -1161,15 +1173,15 @@ index 4be0f29cc..3787dc8fb 100644
11611173 /* Watchdog type1: hardware implementation version1
11621174 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems).
11631175 */
1164- @@ -7670,6 +8481 ,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
1176+ @@ -7670,6 +8493 ,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
11651177 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
11661178 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
11671179 case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET:
11681180+ case MLXPLAT_CPLD_LPC_REG_LED9_OFFSET:
11691181 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
11701182 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET:
11711183 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
1172- @@ -7734,6 +8546 ,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
1184+ @@ -7734,6 +8558 ,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
11731185 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET:
11741186 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
11751187 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
@@ -1178,7 +1190,7 @@ index 4be0f29cc..3787dc8fb 100644
11781190 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
11791191 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:
11801192 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
1181- @@ -7755,6 +8569 ,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
1193+ @@ -7755,6 +8581 ,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
11821194 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:
11831195 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET:
11841196 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
@@ -1187,15 +1199,15 @@ index 4be0f29cc..3787dc8fb 100644
11871199 case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET:
11881200 return true;
11891201 }
1190- @@ -7797,6 +8613 ,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
1202+ @@ -7797,6 +8625 ,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
11911203 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
11921204 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
11931205 case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET:
11941206+ case MLXPLAT_CPLD_LPC_REG_LED9_OFFSET:
11951207 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
11961208 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
11971209 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET:
1198- @@ -7889,6 +8706 ,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
1210+ @@ -7889,6 +8718 ,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
11991211 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET:
12001212 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
12011213 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
@@ -1205,7 +1217,7 @@ index 4be0f29cc..3787dc8fb 100644
12051217 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
12061218 case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET:
12071219 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:
1208- @@ -7948,6 +8768 ,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
1220+ @@ -7948,6 +8780 ,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
12091221 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:
12101222 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET:
12111223 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:
@@ -1215,15 +1227,15 @@ index 4be0f29cc..3787dc8fb 100644
12151227 case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET:
12161228 return true;
12171229 }
1218- @@ -7990,6 +8813 ,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
1230+ @@ -7990,6 +8825 ,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
12191231 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
12201232 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
12211233 case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET:
12221234+ case MLXPLAT_CPLD_LPC_REG_LED9_OFFSET:
12231235 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
12241236 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
12251237 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET:
1226- @@ -8080,6 +8904 ,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
1238+ @@ -8080,6 +8916 ,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
12271239 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET:
12281240 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
12291241 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
@@ -1233,7 +1245,7 @@ index 4be0f29cc..3787dc8fb 100644
12331245 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
12341246 case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET:
12351247 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:
1236- @@ -8133,6 +8960 ,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
1248+ @@ -8133,6 +8972 ,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
12371249 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:
12381250 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET:
12391251 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:
@@ -1243,7 +1255,7 @@ index 4be0f29cc..3787dc8fb 100644
12431255 case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET:
12441256 return true;
12451257 }
1246- @@ -8201,6 +9031 ,17 @@ static const struct reg_default mlxplat_mlxcpld_regmap_smart_switch[] = {
1258+ @@ -8201,6 +9043 ,17 @@ static const struct reg_default mlxplat_mlxcpld_regmap_smart_switch[] = {
12471259 MLXPLAT_CPLD_LPC_SM_SW_MASK },
12481260 };
12491261
@@ -1261,7 +1273,7 @@ index 4be0f29cc..3787dc8fb 100644
12611273 struct mlxplat_mlxcpld_regmap_context {
12621274 void __iomem *base;
12631275 };
1264- @@ -8323,6 +9164 ,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_smart_switch = {
1276+ @@ -8323,6 +9176 ,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_smart_switch = {
12651277 .reg_write = mlxplat_mlxcpld_reg_write,
12661278 };
12671279
@@ -1282,7 +1294,7 @@ index 4be0f29cc..3787dc8fb 100644
12821294 /* Wait completion routine for indirect access for register map */
12831295 static int mlxplat_fpga_completion_wait(struct mlxplat_mlxcpld_regmap_context *ctx)
12841296 {
1285- @@ -8448,6 +9303 ,8 @@ static struct spi_board_info *mlxplat_spi;
1297+ @@ -8448,6 +9315 ,8 @@ static struct spi_board_info *mlxplat_spi;
12861298 static struct pci_dev *lpc_bridge;
12871299 static struct pci_dev *i2c_bridge;
12881300 static struct pci_dev *jtag_bridge;
@@ -1291,7 +1303,7 @@ index 4be0f29cc..3787dc8fb 100644
12911303
12921304 /* Platform default reset function */
12931305 static int mlxplat_reboot_notifier(struct notifier_block *nb, unsigned long action, void *unused)
1294- @@ -8480,6 +9337 ,26 @@ static void mlxplat_poweroff(void)
1306+ @@ -8480,6 +9349 ,26 @@ static void mlxplat_poweroff(void)
12951307 kernel_halt();
12961308 }
12971309
@@ -1318,7 +1330,7 @@ index 4be0f29cc..3787dc8fb 100644
13181330 static int __init mlxplat_register_platform_device(void)
13191331 {
13201332 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1,
1321- @@ -9011,6 +9888 ,38 @@ static int __init mlxplat_dmi_ng400_hi171_matched(const struct dmi_system_id *dm
1333+ @@ -9011,6 +9900 ,38 @@ static int __init mlxplat_dmi_ng400_hi171_matched(const struct dmi_system_id *dm
13221334 return mlxplat_register_platform_device();
13231335 }
13241336
@@ -1357,7 +1369,7 @@ index 4be0f29cc..3787dc8fb 100644
13571369 static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
13581370 {
13591371 .callback = mlxplat_dmi_default_wc_matched,
1360- @@ -9165,6 +10074 ,40 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
1372+ @@ -9165,6 +10086 ,40 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
13611373 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI172"),
13621374 },
13631375 },
@@ -1398,7 +1410,7 @@ index 4be0f29cc..3787dc8fb 100644
13981410 {
13991411 .callback = mlxplat_dmi_msn274x_matched,
14001412 .matches = {
1401- @@ -9253,8 +10196 ,8 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
1413+ @@ -9253,8 +10208 ,8 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
14021414 int shift, i;
14031415
14041416 /* Scan adapters from expected id to verify it is free. */
@@ -1409,7 +1421,7 @@ index 4be0f29cc..3787dc8fb 100644
14091421 mlxplat_max_adap_num; i++) {
14101422 search_adap = i2c_get_adapter(i);
14111423 if (search_adap) {
1412- @@ -9263,7 +10206 ,7 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
1424+ @@ -9263,7 +10218 ,7 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
14131425 }
14141426
14151427 /* Return if expected parent adapter is free. */
@@ -1418,7 +1430,7 @@ index 4be0f29cc..3787dc8fb 100644
14181430 return 0;
14191431 break;
14201432 }
1421- @@ -9285,7 +10228 ,7 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
1433+ @@ -9285,7 +10240 ,7 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
14221434 }
14231435
14241436 /* Shift bus only if mux provided by 'mlxplat_mux_data'. */
@@ -1428,5 +1440,5 @@ index 4be0f29cc..3787dc8fb 100644
14281440
14291441 return 0;
14301442- -
1431- 2.20 .1
1443+ 2.34 .1
14321444
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