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| 1 | +From c5bb10dcd8544a662b4bc81ab8930749e343475f Mon Sep 17 00:00:00 2001 |
| 2 | +From: Oleksandr Shamray < [email protected]> |
| 3 | +Date: Thu, 22 May 2025 19:31:38 +0300 |
| 4 | +Subject: [PATCH] platform: mellanox: Downstream: Add support for Q3401-RD |
| 5 | + Nvidia XDR DGX flavor switch. |
| 6 | + |
| 7 | +This system is based on Nvidia Q3400 Nvidia Quantum-3 36x800Gb/s Switch, with the |
| 8 | +following key changes: |
| 9 | + |
| 10 | +Key changes: |
| 11 | +- New Power Supply: AC/DC PSUs power repaced by rack busbar input power ORv3 DC 48V-54V. |
| 12 | +- Dimensions MGX/DGX 1U compliance Tool-less top cover (fast cover opening with no screw) |
| 13 | +- Air Cooled: 7 + 1 redundant fan units C2P not reversable 80x80mm 48V (instead of 9 +1 60x60mm) |
| 14 | + |
| 15 | +Signed-off-by: Oleksandr Shamray < [email protected]> |
| 16 | +--- |
| 17 | + drivers/platform/mellanox/mlx-platform.c | 144 +++++++++++++++++++++++++++++-- |
| 18 | + 1 file changed, 137 insertions(+), 7 deletions(-) |
| 19 | + |
| 20 | +diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c |
| 21 | +index d71f254..fa8c92c 100644 |
| 22 | +--- a/drivers/platform/mellanox/mlx-platform.c |
| 23 | ++++ b/drivers/platform/mellanox/mlx-platform.c |
| 24 | +@@ -719,9 +719,9 @@ static struct i2c_mux_reg_platform_data mlxplat_ng800_mux_data[] = { |
| 25 | + .values = mlxplat_msn21xx_channels, |
| 26 | + .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), |
| 27 | + }, |
| 28 | +- |
| 29 | + }; |
| 30 | + |
| 31 | ++ |
| 32 | + /* Platform channels for XDR system family */ |
| 33 | + static const int mlxplat_xdr_channels[] = { |
| 34 | + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, |
| 35 | +@@ -754,6 +754,40 @@ static struct i2c_mux_reg_platform_data mlxplat_xdr_mux_data[] = { |
| 36 | + }, |
| 37 | + }; |
| 38 | + |
| 39 | ++/* Platform XDR mux data with separated CPU bus adapter id */ |
| 40 | ++static struct i2c_mux_reg_platform_data mlxplat_xdr_ext_mux_data[] = { |
| 41 | ++ { |
| 42 | ++ .parent = 1, |
| 43 | ++ .base_nr = MLXPLAT_CPLD_CH1, |
| 44 | ++ .write_only = 1, |
| 45 | ++ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, |
| 46 | ++ .reg_size = 1, |
| 47 | ++ .idle_in_use = 1, |
| 48 | ++ .values = mlxplat_xdr_channels, |
| 49 | ++ .n_values = ARRAY_SIZE(mlxplat_xdr_channels), |
| 50 | ++ }, |
| 51 | ++ { |
| 52 | ++ .parent = 1, |
| 53 | ++ .base_nr = MLXPLAT_CPLD_CH2_XDR, |
| 54 | ++ .write_only = 1, |
| 55 | ++ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, |
| 56 | ++ .reg_size = 1, |
| 57 | ++ .idle_in_use = 1, |
| 58 | ++ .values = mlxplat_modular_upper_channel, |
| 59 | ++ .n_values = ARRAY_SIZE(mlxplat_modular_upper_channel), |
| 60 | ++ }, |
| 61 | ++ { |
| 62 | ++ .parent = MLXPLAT_CPLD_CH2_XDR, |
| 63 | ++ .base_nr = MLXPLAT_CPLD_CH2_XDR+1, |
| 64 | ++ .write_only = 1, |
| 65 | ++ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, |
| 66 | ++ .reg_size = 1, |
| 67 | ++ .idle_in_use = 1, |
| 68 | ++ .values = mlxplat_msn21xx_channels, |
| 69 | ++ .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), |
| 70 | ++ }, |
| 71 | ++}; |
| 72 | ++ |
| 73 | + /* Platform channels for L1 scale out system family */ |
| 74 | + static const int mlxplat_l1_scale_out_channels[] = { |
| 75 | + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, |
| 76 | +@@ -2183,6 +2217,82 @@ static struct mlxreg_core_item mlxplat_mlxcpld_xdr_items[] = { |
| 77 | + }, |
| 78 | + }; |
| 79 | + |
| 80 | ++static struct mlxreg_core_item mlxplat_mlxcpld_xdr_dgx_items[] = { |
| 81 | ++ { |
| 82 | ++ .data = mlxplat_mlxcpld_dgx_psu_items_data, |
| 83 | ++ .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF, |
| 84 | ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, |
| 85 | ++ .mask = MLXPLAT_CPLD_PSU_MASK, |
| 86 | ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_dgx_psu_items_data), |
| 87 | ++ .inversed = 1, |
| 88 | ++ .health = false, |
| 89 | ++ }, |
| 90 | ++ { |
| 91 | ++ .data = mlxplat_mlxcpld_dgx_pwr_items_data, |
| 92 | ++ .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, |
| 93 | ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, |
| 94 | ++ .mask = MLXPLAT_CPLD_PWR_MASK, |
| 95 | ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_dgx_pwr_items_data), |
| 96 | ++ .inversed = 0, |
| 97 | ++ .health = false, |
| 98 | ++ }, |
| 99 | ++ { |
| 100 | ++ .data = mlxplat_mlxcpld_xdr_fan_items_data, |
| 101 | ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, |
| 102 | ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, |
| 103 | ++ .mask = MLXPLAT_CPLD_FAN_XDR_MASK, |
| 104 | ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, |
| 105 | ++ .capability_mask = MLXPLAT_CPLD_FAN_CAP_MASK, |
| 106 | ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), |
| 107 | ++ .inversed = 1, |
| 108 | ++ .health = false, |
| 109 | ++ }, |
| 110 | ++ { |
| 111 | ++ .data = mlxplat_mlxcpld_xdr_asic1_items_data, |
| 112 | ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, |
| 113 | ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, |
| 114 | ++ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, |
| 115 | ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, |
| 116 | ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, |
| 117 | ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic1_items_data), |
| 118 | ++ .inversed = 0, |
| 119 | ++ .health = true, |
| 120 | ++ }, |
| 121 | ++ { |
| 122 | ++ .data = mlxplat_mlxcpld_xdr_asic2_items_data, |
| 123 | ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, |
| 124 | ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, |
| 125 | ++ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, |
| 126 | ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, |
| 127 | ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, |
| 128 | ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic2_items_data), |
| 129 | ++ .inversed = 0, |
| 130 | ++ .health = true, |
| 131 | ++ }, |
| 132 | ++ { |
| 133 | ++ .data = mlxplat_mlxcpld_xdr_asic3_items_data, |
| 134 | ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, |
| 135 | ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET, |
| 136 | ++ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, |
| 137 | ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, |
| 138 | ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, |
| 139 | ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic3_items_data), |
| 140 | ++ .inversed = 0, |
| 141 | ++ .health = true, |
| 142 | ++ }, |
| 143 | ++ { |
| 144 | ++ .data = mlxplat_mlxcpld_xdr_asic4_items_data, |
| 145 | ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, |
| 146 | ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET, |
| 147 | ++ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, |
| 148 | ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, |
| 149 | ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, |
| 150 | ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic4_items_data), |
| 151 | ++ .inversed = 0, |
| 152 | ++ .health = true, |
| 153 | ++ }, |
| 154 | ++}; |
| 155 | ++ |
| 156 | + static struct mlxreg_core_data mlxplat_mlxcpld_leakage_items_data[] = { |
| 157 | + { |
| 158 | + .label = "leakage1", |
| 159 | +@@ -2350,6 +2460,17 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_xdr_liq_data = { |
| 160 | + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_FRU | MLXPLAT_CPLD_LOW_AGGR_MASK_MULTI_ASICS, |
| 161 | + }; |
| 162 | + |
| 163 | ++static |
| 164 | ++struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_xdr_dgx_data = { |
| 165 | ++ .items = mlxplat_mlxcpld_xdr_dgx_items, |
| 166 | ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_dgx_items), |
| 167 | ++ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, |
| 168 | ++ .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, |
| 169 | ++ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, |
| 170 | ++ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_FRU | MLXPLAT_CPLD_LOW_AGGR_MASK_MULTI_ASICS, |
| 171 | ++}; |
| 172 | ++ |
| 173 | ++ |
| 174 | + static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { |
| 175 | + { |
| 176 | + .label = "pwr1", |
| 177 | +@@ -10103,15 +10224,24 @@ static int __init mlxplat_dmi_xdr_matched(const struct dmi_system_id *dmi) |
| 178 | + mlxplat_mlxcpld_xdr_pwr_items_data[i].hpdev.nr = |
| 179 | + mlxplat_mlxcpld_xdr_pwr_nr_fixup[i]; |
| 180 | + } |
| 181 | ++ if (!strcmp(sku, "HI179")) { |
| 182 | ++ mlxplat_hotplug = &mlxplat_mlxcpld_xdr_dgx_data; |
| 183 | ++ mlxplat_hotplug->deferred_nr = |
| 184 | ++ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; |
| 185 | ++ mlxplat_regs_io = &mlxplat_dgx_ng_regs_io_data; |
| 186 | ++ mlxplat_mux_num = ARRAY_SIZE(mlxplat_xdr_ext_mux_data); |
| 187 | ++ mlxplat_mux_data = mlxplat_xdr_ext_mux_data; |
| 188 | ++ } else { |
| 189 | ++ mlxplat_hotplug = &mlxplat_mlxcpld_xdr_data; |
| 190 | ++ mlxplat_hotplug->deferred_nr = |
| 191 | ++ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; |
| 192 | ++ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; |
| 193 | ++ mlxplat_mux_num = ARRAY_SIZE(mlxplat_xdr_mux_data); |
| 194 | ++ mlxplat_mux_data = mlxplat_xdr_mux_data; |
| 195 | ++ } |
| 196 | + |
| 197 | + mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; |
| 198 | +- mlxplat_mux_num = ARRAY_SIZE(mlxplat_xdr_mux_data); |
| 199 | +- mlxplat_mux_data = mlxplat_xdr_mux_data; |
| 200 | +- mlxplat_hotplug = &mlxplat_mlxcpld_xdr_data; |
| 201 | +- mlxplat_hotplug->deferred_nr = |
| 202 | +- mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; |
| 203 | + mlxplat_led = &mlxplat_xdr_led_data; |
| 204 | +- mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; |
| 205 | + mlxplat_fan = &mlxplat_xdr_fan_data; |
| 206 | + for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) |
| 207 | + mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; |
| 208 | +-- |
| 209 | +2.8.4 |
| 210 | + |
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