hw: Improve the cdc check and configuration

Author: Lore0599

Makefile

@@ -9,7 +9,7 @@
 CHIM_ROOT ?= $(shell pwd)
 
 # Tooling
-BENDER                 = bender-0.28.2	-d $(CHIM_ROOT)
+BENDER                 ?= bender -d $(CHIM_ROOT)
 VERIBLE_VERILOG_FORMAT ?= $(CHIM_UTILS_DIR)/verible-verilog/verible-verilog-format
 
 # Set dependency paths only if dependencies have already been cloned

hw/chimera_clu_domain.sv

@@ -185,7 +185,8 @@ module chimera_clu_domain
         .narrow_out_req_t (narrow_out_req_t),
         .narrow_out_resp_t(narrow_out_resp_t),
         .wide_out_req_t   (wide_out_req_t),
-        .wide_out_resp_t  (wide_out_resp_t)
+        .wide_out_resp_t  (wide_out_resp_t),
+        .EnAxiCdc         (ChimeraClusterCfg.EnAxiCdc[extClusterIdx])
       ) i_chimera_cluster (
         .soc_clk_i(soc_clk_i),
         .clu_clk_i(clu_clk_i),

hw/chimera_pkg.sv

@@ -30,6 +30,7 @@ package chimera_pkg;
     logic [iomsb(ExtClusters):0]          hasWideMasterPort;
     byte_bt [iomsb(ExtClusters):0]        NrCores;
     cluster_type_e [iomsb(ExtClusters):0] ClusterType;
+    logic[iomsb(ExtClusters):0]           EnAxiCdc;
   } cluster_config_t;
 
   // For each instantiated cluster, you need to specify three parameters:
@@ -40,7 +41,8 @@ package chimera_pkg;
   localparam cluster_config_t ChimeraClusterCfg = '{
       hasWideMasterPort: {1'b1, 1'b1, 1'b1, 1'b1, 1'b1},
       NrCores: {8'h9, 8'h9, 8'h9, 8'h9, 8'h9},
-      ClusterType: {SNITCH, SNITCH, SNITCH, SNITCH, SNITCH}
+      ClusterType: {SNITCH, SNITCH, SNITCH, SNITCH, SNITCH},
+      EnAxiCdc: {1'b1, 1'b1, 1'b1, 1'b1, 1'b1}
   };
 
   function automatic int _sumVector(byte_bt [iomsb(ExtClusters):0] vector, int vectorLen);

hw/chimera_top_wrapper.sv

@@ -315,7 +315,7 @@ module chimera_top_wrapper
   // This is the enable clk gate, i.e.
   // - enable = 1 -> clock is gated (off)
   // - enable = 0 -> clock is running (on)
-  // It will be used to drive the actual clk eneable signal ine ach cluster.
+  // It will be used to drive the actual clk eneable signal in each cluster.
   // For this reason it's inverted when connected to the cluster.
   assign cluster_clock_gate_en = {
     reg2hw.cluster_4_clk_gate_en,
@@ -336,7 +336,6 @@ module chimera_top_wrapper
     ~reg2hw.reset_cluster_0.q
   };
 
-  // TODO: Double check that teh logic AND is sufficient!
   // The Rst used for each cluster is the AND gate among all different source of rst in the system that are:
   // - rst_ni: Global asynchronous reset coming from the PAD
   // - cluster_soft_rst_n: Software synchronous rst coming from the SoC configuration registers

hw/clusters/chimera_cluster.sv

@@ -17,7 +17,8 @@ module chimera_cluster
   parameter type         narrow_out_req_t  = logic,
   parameter type         narrow_out_resp_t = logic,
   parameter type         wide_out_req_t    = logic,
-  parameter type         wide_out_resp_t   = logic
+  parameter type         wide_out_resp_t   = logic,
+  parameter bit          EnAxiCdc          = 0
 ) (
   input  logic                                        soc_clk_i,
   input  logic                                        clu_clk_i,
@@ -192,7 +193,7 @@ module chimera_cluster
     .clu_wide_out_req_t (axi_cluster_out_wide_req_t),
     .clu_wide_out_resp_t(axi_cluster_out_wide_resp_t),
     // Make sure the SoC and Clusters run at the same frequency if CDCs are disabled
-    .EnAxiCdc (1'b0)
+    .EnAxiCdc (EnAxiCdc)
 
   ) i_cluster_axi_adapter (
     .soc_clk_i(soc_clk_i),

iis-env.sh

@@ -3,17 +3,17 @@
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 
+export BENDER='bender-0.29.1'
 export VSIM="questa-2022.3 vsim"
 export VOPT="questa-2022.3 vopt"
 export VLIB="questa-2022.3 vlib"
 export BASE_PYTHON=/usr/local/anaconda3/bin/python3.11
-export CHS_SW_GCC_BINROOT=/usr/pack/riscv-1.0-kgf/riscv64-gcc-12.2.0/bin
+export CHS_SW_32_GCC_BINROOT=/usr/pack/riscv-1.0-kgf/default/bin
 export RISCV_GCC_BINROOT=/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0/bin
 export CC=/usr/pack/gcc-11.2.0-af/linux-x64/bin/gcc
 export CXX=/usr/pack/gcc-11.2.0-af/linux-x64/bin/g++
 export CMAKE=cmake-3.28.3
 export SN_LLVM_BINROOT=/usr/scratch2/vulcano/colluca/tools/riscv32-snitch-llvm-almalinux8-15.0.0-snitch-0.2.0/bin
-export BENDER='bender-0.29.1'
 
 # Create the python venv
 if [ ! -d ".venv" ]; then

target/sim/src/fixture_chimera_soc.sv

@@ -22,6 +22,8 @@ module fixture_chimera_soc #(
 
   localparam chimera_cfg_t DutCfg = ChimeraCfg[SelectedCfg];
   localparam cheshire_cfg_t ChsCfg = DutCfg.ChsCfg;
+  localparam time         ClkPeriodClu           = 2ns;
+  localparam time         ClkPeriodSys           = 5ns;
 
   `CHESHIRE_TYPEDEF_ALL(, ChsCfg)
   `CHIMERA_TYPEDEF_ALL(, DutCfg)
@@ -157,6 +159,8 @@ module fixture_chimera_soc #(
 
   vip_chimera_soc #(
     .DutCfg                (ChsCfg),
+    .ClkPeriodClu          (ClkPeriodClu),
+    .ClkPeriodSys          (ClkPeriodSys),
     // Determine whether we preload the hyperram model or not User preload. If 0, the memory model
     // is not preloaded at time 0.
     .HypUserPreload        (`HYP_USER_PRELOAD),
@@ -169,4 +173,16 @@ module fixture_chimera_soc #(
     .*
   );
 
+
+  //////////////////
+  //  CDCs check  //
+  /////////////////
+  initial begin
+  for (int extClusterIdx = 0; extClusterIdx < ExtClusters; extClusterIdx++) begin: gen_cdc_check
+    if (!ChimeraClusterCfg.EnAxiCdc[extClusterIdx] && (ClkPeriodClu != ClkPeriodSys)) begin
+      $fatal(1, "ClusterIdx:%d, EnAxiCDC = %d: Missing CDCs", extClusterIdx, ChimeraClusterCfg.EnAxiCdc[extClusterIdx]);
+    end
+  end
+end
+
 endmodule

target/sim/src/vip_chimera_soc.sv

@@ -21,7 +21,7 @@ module vip_chimera_soc
   parameter type         axi_ext_mst_rsp_t      = logic,
   // Timing
   parameter time         ClkPeriodClu           = 2ns,
-  parameter time         ClkPeriodSys           = 2ns,
+  parameter time         ClkPeriodSys           = 5ns,
   parameter time         ClkPeriodJtag          = 20ns,
   parameter time         ClkPeriodRtc           = 30518ns,
   parameter int unsigned RstCycles              = 5,