cross-repo: wire silicon-bridge NIR I/O to depend on nir-rs (org interop — not crate 0.5.0)

[rmems]

Summary

Org interop / adoption (not a nir-rs crate release): silicon-bridge depends on nir-rs for IR parse/serialize; keep FPGA mapping (Q8.8, .mem) local.

Versioning

• Depend on crate 0.4.x (git/path or future crates.io). Completing this issue does not mean publish or tag nir-rs 0.5.0.
• Crate semver moves only when nir-rs public API/behavior changes for all users. This ticket is consumer wiring in silicon-bridge.
• If wiring surfaces a library bug/gap, open a nir-rs fix → typically 0.4.y patch, not a new minor solely for Limen.

Boundary

nir-rs owns	silicon-bridge owns
Typed graph + 17 nodes	Q8.8 fixed-point
HDF5 .nir read/write	.mem / Vivado params
Round-trip IR fidelity	Map NirGraph → thresholds/weights/decay
Spec / version / errors	Unsupported-node policy for FPGA

Do not add hdf5 to silicon-bridge or duplicate the 17-node decoder.

Dependency

[dependencies]
nir-rs = { git = "https://github.com/Limen-Neural/nir-rs", branch = "main", optional = true }
# Prefer pin by rev/tag once tagged, e.g. tag = "v0.4.0"

[features]
nir = ["dep:nir-rs"]

Adapter sketch

impl FpgaParameterExporter {
    pub fn from_nir(graph: &nir_rs::NirGraph) -> Result<Self, MapError>;
}

Ordering

• Library prerequisites: done (crate 0.2 graph, 0.3 I/O, 0.4 DX on main)
• In-memory mapping tests: unblocked
• End-to-end .nir → .mem: unblocked (nir_rs::read / write available)
• Primary code path: silicon-bridge repo, not new features in nir-rs

LIM-772 migration

Reassign HDF5 AC to nir-rs; keep Q8.8/.mem/FPGA mapping on silicon-bridge. AC becomes “loads via nir_rs::read”.

Related

• Consumer: feat: NIR (Neuromorphic Intermediate Representation) integration — read/write support rmems/silicon-bridge#15 · LIM-772
• Linear: https://linear.app/rpd-34/issue/LIM-835
• Sibling exporters: cross-repo: wire axon-encoder / engram-parser exporters to nir-rs (org interop — not crate 0.5.0) #16 · LIM-831
• Org epic: LIM-776 · Parent: Epic: pure-Rust NIR (reusable crate + org adoption) #1 / LIM-822

---

Updated 2026-08-06 by Grok Build: Grok 4.5 (medium) (xAI) via GitHub MCP — clarified org interop vs crate semver; library prereqs unblocked.

[linear-code]

LIM-835

[rmems]

Research: silicon-bridge ↔ nir-rs interop (v0.5)

Evidence-based wiring plan. Full write-up: session artifact swarm/research/v0.5-interop.md.

Boundary (hard)

nir-rs owns	silicon-bridge owns
Typed graph + 17 nodes	Q8.8 fixed-point
HDF5 .nir read/write	.mem / Vivado params
Round-trip IR fidelity	Map NirGraph → thresholds/weights/decay
Spec/version/errors	Unsupported-node policy for FPGA

Do not add hdf5 to silicon-bridge. LIM-772 / silicon-bridge#15 must depend on this crate for parse/serialize.

Dependency pattern (org conventions)

Match plasticity-lab / brainstem-daemon (git until crates.io):

[dependencies]
nir-rs = { git = "https://github.com/Limen-Neural/nir-rs", branch = "main", optional = true }

[features]
nir = ["dep:nir-rs"]

Local monorepo: path = "../nir-rs" for dev only.

Minimal API surface needed from nir-rs

• NirGraph, node/edge types, all 17 node param structs (v0.2 feat: typed NIR graph model (nodes, edges, metadata, version) #7/feat: implement all 17 NIR node types #8)
• read(path) -> Result<NirGraph>, write(path, &graph) (v0.3 feat: HDF5 read path (.nir → graph) #9/feat: HDF5 write path (graph → .nir) #10)
• NirError (v0.2 feat: structured errors (unknown nodes, version skew, I/O) #12)

silicon-bridge adapter sketch

// feature = "nir"
impl FpgaParameterExporter {
    pub fn from_nir(graph: &nir_rs::NirGraph) -> Result<Self, MapError>;
}

pub fn load_nir_to_mem(path, out_dir) -> Result<()> {
    let g = nir_rs::read(path)?;
    FpgaParameterExporter::from_nir(&g)?.export_to_mem_files(out_dir)
}

Map: LIF/IF/Threshold → thresholds+decay; Linear/Affine → weights; else MapError::Unsupported.

Ordering

Work	Gate
In-memory mapping unit tests	v0.2 Core IR
.nir → .mem integration	v0.3 HDF5 I/O (hard)
This issue complete	After #9/#10/#11 green

Block consumer Cargo.toml wiring until v0.3 I/O exists.

LIM-772 migration

1. Reassign HDF5 items on LIM-772 to nir-rs (feat: HDF5 read path (.nir → graph) #9/feat: HDF5 write path (graph → .nir) #10/test: round-trip fidelity + NIR fixtures #11).
2. Keep FPGA mapping + Q8.8 + .mem on silicon-bridge.
3. Rewrite AC: “loads via nir_rs::read”, not “implements 17-node HDF5 decoder”.

Cross-links

• Consumer: silicon-bridge#15 / LIM-772
• Linear: LIM-835
• Sibling exporters: cross-repo: wire axon-encoder / engram-parser exporters to nir-rs (org interop — not crate 0.5.0) #16 / LIM-831
• Org epic: LIM-776
• nir-rs epic: Epic: pure-Rust NIR (reusable crate + org adoption) #1 / LIM-822

[rmems]

Research notes (swarm 2026-07-22)

Refresh after Core IR (v0.2) landed on Main @ ea8c338 (package 0.2.0, PR #18). Full write-up: swarm/research/2026-07-22-refresh-v0.5.md (prior: v0.5-interop.md).

What changed vs 2026-07-21

Topic	Now
Core IR	Usable — NirGraph, closed NirNode, Tensor, NirError
HDF5 I/O	Still stubs: nir_rs::io::read / write → NirError::Unimplemented (#9/#10/#11 open)
crates.io	Not published — no tags/releases; use git
Default branch	Main (capital M) — not main

Consume now (in-memory)

silicon-bridge can implement / unit-test FpgaParameterExporter::from_nir(&NirGraph) against real types:

use nir_rs::{NirGraph, NirNode};
// node params: nir_rs::nodes::{Lif, Linear, Affine, Threshold, …}
// match NirNode exhaustively — enum is intentionally NOT #[non_exhaustive]

Map (refined): Lif/If/Threshold → thresholds (+ decay from tau); Linear/Affine → weights; CubaLif/CubaLi → dual-tau policy TBD; Conv*, pools, nested Graph → structured Unsupported until FPGA path exists.

Do not add hdf5 here. Do not use aliases (CurrLIF, Convolution, SumPooling).

Still hard-blocked on v0.3 for closing this issue

Work	Gate
.nir → .mem E2E via nir_rs::io::read	#9 (LIM-827)
Optional export-back via io::write	#10 (LIM-833)
IR round-trip fixtures	#11

Linear already: LIM-835 blockedBy LIM-827 / LIM-833.

Dependency (corrected)

[dependencies]
nir-rs = { git = "https://github.com/Limen-Neural/nir-rs", branch = "Main", optional = true }
# prefer rev pin for CI once adapting:
# nir-rs = { git = "https://github.com/Limen-Neural/nir-rs", rev = "ea8c3388b3e6a504f1bab904811f107c24d97fb9", optional = true }

[features]
nir = ["dep:nir-rs"]

Revision of prior hard rule: a feature-gated git dep for in-memory mapping tests is OK now. Claiming integration complete / E2E still waits for v0.3.

I/O path note

Crate root does not re-export I/O — use nir_rs::io::read / nir_rs::io::write (not nir_rs::read).

LIM-772 / silicon-bridge#15

Consumer issue still documents in-crate HDF5 + obsolete wire names. When work starts, rewrite AC to “loads via nir_rs::io::read” and exhaustive map of closed NirNode.

Cross-links

• Linear: LIM-835
• Consumer: silicon-bridge#15 / LIM-772
• Sibling exporters: cross-repo: wire axon-encoder / engram-parser exporters to nir-rs (org interop — not crate 0.5.0) #16 / LIM-831
• v0.3: feat: HDF5 read path (.nir → graph) #9 / feat: HDF5 write path (graph → .nir) #10 / test: round-trip fidelity + NIR fixtures #11