Bitstream for GOWIN FPGA

[dev-hack95]

Does pipelineC generate bitstream for GOWIN FPGA

[dev-hack95]

Its not generating pnr

[JulianKemmerer]

It does not generate bitstreams.

I will run PNR if configured to do so

PipelineC/src/GOWIN.py

Line 19 in 423306e

DO_PNR = None # None|"all"

but it has been a while since folks have run that tool, I forget if one mode vs the other was fully working

still experimental

[dev-hack95]

https://github.com/YosysHQ/apicula.git

Can't we use this should I write code to generate bitstream it's experimental though

[JulianKemmerer]

Absolutely hack away doing whatever you want - love hearing ideas. Come over to the Discord to chat if you like 🤓

But the starting limitation to producing a final bitstream for a board is that pipelinec does not know two critical things for making the final bitstream:

1. the mapping of HDL signals to pins (constraints file)
2. how to instantiate and configure PLLs and such that generate clocks the user needs
   (3) sorta like 2^ more generally, if your design needs to instantiate anything outside of pipelinec for whatever reason, you typically do that by hand as you build .bit, some things involving certain FPGA macros/buffers/etc sometimes need this)