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Hey there 👋 you are close to having the right code. Yes PipelineC supports floating point math and will autopipeline for you. Faster target clock rates will require more pipeline stages / longer latency. The tool first produces VHDL, and then another conversion layer --verilog via open source ghdl and yosys tools can produce Verilog.

First minor point is no pointers, all compile time fixed size arrays (i.e. #define SIZE stuff typically).

Important things to note is the static float shift_reg[N] state causes the entire function it lives inside to not be pipelined. So the first thing we've done before is wrap that static shifting window in its own function. Looking like (using a stream with…

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Answer selected by JulianKemmerer
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Converted from issue

This discussion was converted from issue #207 on October 02, 2024 15:08.