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Groupsun/README.md

Hi, I am SunnyChen

  • 🔭 I’m currently working as a CPU design Engineer, mostly play around with RISC-V
  • 🌱 I’m currently working & learning processor front-end designs (such as branch prediction) and cache related things (such as hardware prefetch)

Things I code with

How to reach me

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  1. riscv-mini-five-stage riscv-mini-five-stage Public

    This is my graduation project, a simple processor soft core, which implements RV32I ISA.

    Scala 17 1

  2. SCUT_2018Fall_Intelligent_Robot SCUT_2018Fall_Intelligent_Robot Public

    华南理工大学-2018年秋-智能机器人技术-大作业

    C 7

  3. Verilator_Simple_Usage Verilator_Simple_Usage Public

    A simple verilator usage

    C++ 4 3

  4. xv6-riscv xv6-riscv Public

    Forked from mit-pdos/xv6-riscv

    Xv6 for RISC-V

    C

  5. RSSNext/Folo RSSNext/Folo Public

    🧡 Follow everything in one place

    TypeScript 29.9k 1.3k

  6. Notebook Notebook Public

    My own notebook.

    C 4 1