From d71a1acb4f34ce8d65e8ae6c644e4de746e4a2de Mon Sep 17 00:00:00 2001 From: Pierre-Olivier Vauboin Date: Thu, 21 Jul 2022 15:02:21 +0200 Subject: [PATCH] Decoder jtag: append to list in constant time This improves the decoding speed a lot (x50). Previously 98% of the run time was spent in list.insert(). --- libsigrokdecode4DSL/decoders/jtag/pd.py | 45 ++++++++++++++----------- 1 file changed, 25 insertions(+), 20 deletions(-) mode change 100644 => 100755 libsigrokdecode4DSL/decoders/jtag/pd.py diff --git a/libsigrokdecode4DSL/decoders/jtag/pd.py b/libsigrokdecode4DSL/decoders/jtag/pd.py old mode 100644 new mode 100755 index e9c629b6..8de8f5d1 --- a/libsigrokdecode4DSL/decoders/jtag/pd.py +++ b/libsigrokdecode4DSL/decoders/jtag/pd.py @@ -200,18 +200,18 @@ def handle_rising_tck_edge(self, tdi, tdo, tck, tms, trst, srst, rtck): self.ss_bitstring = self.samplenum if self.bits_cnt > 1: - self.putx([16, [str(self.bits_tdi[0])]]) - self.putx([17, [str(self.bits_tdo[0])]]) + self.putx([16, [str(self.bits_tdi[-1])]]) + self.putx([17, [str(self.bits_tdo[-1])]]) # Use self.samplenum as ES of the previous bit. - self.bits_samplenums_tdi[0][1] = self.samplenum - self.bits_samplenums_tdo[0][1] = self.samplenum + self.bits_samplenums_tdi[-1][1] = self.samplenum + self.bits_samplenums_tdo[-1][1] = self.samplenum - self.bits_tdi.insert(0, tdi) - self.bits_tdo.insert(0, tdo) + self.bits_tdi.append(tdi) + self.bits_tdo.append(tdo) # Use self.samplenum as SS of the current bit. - self.bits_samplenums_tdi.insert(0, [self.samplenum, -1]) - self.bits_samplenums_tdo.insert(0, [self.samplenum, -1]) + self.bits_samplenums_tdi.append([self.samplenum, -1]) + self.bits_samplenums_tdo.append([self.samplenum, -1]) self.bits_cnt = self.bits_cnt + 1 @@ -223,25 +223,25 @@ def handle_rising_tck_edge(self, tdi, tdo, tck, tms, trst, srst, rtck): if self.bits_cnt > 0: if self.bits_cnt == 1: # Only shift one bit self.ss_bitstring = self.samplenum - self.bits_tdi.insert(0, tdi) - self.bits_tdo.insert(0, tdo) + self.bits_tdi.append(tdi) + self.bits_tdo.append(tdo) ## Use self.samplenum as SS of the current bit. - self.bits_samplenums_tdi.insert(0, [self.samplenum, -1]) - self.bits_samplenums_tdo.insert(0, [self.samplenum, -1]) + self.bits_samplenums_tdi.append([self.samplenum, -1]) + self.bits_samplenums_tdo.append([self.samplenum, -1]) else: ### ---------------------------------------------------------------- - self.putx([16, [str(self.bits_tdi[0])]]) - self.putx([17, [str(self.bits_tdo[0])]]) + self.putx([16, [str(self.bits_tdi[-1])]]) + self.putx([17, [str(self.bits_tdo[-1])]]) ### Use self.samplenum as ES of the previous bit. - self.bits_samplenums_tdi[0][1] = self.samplenum - self.bits_samplenums_tdo[0][1] = self.samplenum + self.bits_samplenums_tdi[-1][1] = self.samplenum + self.bits_samplenums_tdo[-1][1] = self.samplenum - self.bits_tdi.insert(0, tdi) - self.bits_tdo.insert(0, tdo) + self.bits_tdi.append(tdi) + self.bits_tdo.append(tdo) ## Use self.samplenum as SS of the current bit. - self.bits_samplenums_tdi.insert(0, [self.samplenum, -1]) - self.bits_samplenums_tdo.insert(0, [self.samplenum, -1]) + self.bits_samplenums_tdi.append([self.samplenum, -1]) + self.bits_samplenums_tdo.append([self.samplenum, -1]) ## ---------------------------------------------------------------- self.data_ready = True @@ -253,7 +253,10 @@ def handle_rising_tck_edge(self, tdi, tdo, tck, tms, trst, srst, rtck): if self.data_ready: self.data_ready = False self.es_bitstring = self.samplenum + t = self.state[-2:] + ' TDI' + self.bits_tdi.reverse() + self.bits_samplenums_tdi.reverse() b = ''.join(map(str, self.bits_tdi)) h = ' (0x%X' % int('0b' + b, 2) + ')' s = t + ': ' + h + ', ' + str(len(self.bits_tdi)) + ' bits' #b + @@ -265,6 +268,8 @@ def handle_rising_tck_edge(self, tdi, tdo, tck, tms, trst, srst, rtck): self.bits_samplenums_tdi = [] t = self.state[-2:] + ' TDO' + self.bits_tdo.reverse() + self.bits_samplenums_tdo.reverse() b = ''.join(map(str, self.bits_tdo)) h = ' (0x%X' % int('0b' + b, 2) + ')' s = t + ': ' + h + ', ' + str(len(self.bits_tdo)) + ' bits' #+ b