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| 1 | +/* |
| 2 | + * Copyright (c) 2018 Intel Corporation |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | +#include "serial.h" |
| 7 | +#include "vgacon.h" |
| 8 | +#include "printf.h" |
| 9 | +#include "xuk.h" |
| 10 | + |
| 11 | +/* Tiny demonstration of the core64 code. Implements enough of an |
| 12 | + * "OS" layer to do some simple unit testing. |
| 13 | + */ |
| 14 | + |
| 15 | +static void putchar(int c) |
| 16 | +{ |
| 17 | + serial_putc(c); |
| 18 | + vgacon_putc(c); |
| 19 | +} |
| 20 | + |
| 21 | +void test_timers(void) |
| 22 | +{ |
| 23 | + /* Quickly calibrate the timers against each other. Note that |
| 24 | + * the APIC is counting DOWN instead of up! Seems like on |
| 25 | + * qemu, the APIC base frequency is 3.7x slower than the tsc. |
| 26 | + * Looking at source, it seems like APIC is uniformly shifted |
| 27 | + * down from a nominal 1Ghz reference |
| 28 | + * (i.e. qemu_get_time_ns()), where the TSC is based on |
| 29 | + * cpu_get_ticks() and thus pulls in wall clock time & such. |
| 30 | + * If you specify "-icount shift=1", then they synchronize |
| 31 | + * properly. |
| 32 | + */ |
| 33 | + int tsc0, apic0, tsc1, apic1; |
| 34 | + |
| 35 | + __asm__ volatile("rdtsc" : "=a"(tsc0) : : "rdx"); |
| 36 | + apic0 = _apic.CURR_COUNT; |
| 37 | + do { |
| 38 | + /* Qemu misbehaves if I spam these registers. */ |
| 39 | + for (int i = 0; i < 1000; i++) { |
| 40 | + __asm__ volatile("nop"); |
| 41 | + } |
| 42 | + |
| 43 | + __asm__ volatile("rdtsc" : "=a"(tsc1) : : "rdx"); |
| 44 | + apic1 = _apic.CURR_COUNT; |
| 45 | + } while ((tsc1 - tsc0) < 10000 || (apic0 - apic1) < 10000); |
| 46 | + printf("tsc %d apic %d\n", tsc1 - tsc0, apic0 - apic1); |
| 47 | +} |
| 48 | + |
| 49 | +unsigned int _init_cpu_stack(int cpu) |
| 50 | +{ |
| 51 | + return (long)alloc_page(0) + 4096; |
| 52 | +} |
| 53 | + |
| 54 | +void handler_timer(void *arg, int err) |
| 55 | +{ |
| 56 | + printf("Timer expired on CPU%d\n", (int)(long)xuk_get_f_ptr()); |
| 57 | +} |
| 58 | + |
| 59 | +void handler_f3(void *arg, int err) |
| 60 | +{ |
| 61 | + printf("f3 handler on cpu%d arg %x, triggering INT 0xff\n", |
| 62 | + (int)(long)xuk_get_f_ptr(), (int)(long)arg); |
| 63 | + __asm__ volatile("int $0xff"); |
| 64 | + printf("end f3 handler\n"); |
| 65 | +} |
| 66 | + |
| 67 | +void _unhandled_vector(int vector, int err, struct xuk_entry_frame *f) |
| 68 | +{ |
| 69 | + (void)f; |
| 70 | + _putchar = putchar; |
| 71 | + printf("Unhandled vector %d (err %xh) on CPU%d\n", |
| 72 | + vector, err, (int)(long)xuk_get_f_ptr()); |
| 73 | +} |
| 74 | + |
| 75 | +void _isr_entry(void) |
| 76 | +{ |
| 77 | +} |
| 78 | + |
| 79 | +void *_isr_exit_restore_stack(void *interrupted) |
| 80 | +{ |
| 81 | + /* Somewhat hacky test of the ISR exit modes. Two ways of |
| 82 | + * specifying "this stack", one of which does the full spill |
| 83 | + * and restore and one shortcuts that due to the NULL |
| 84 | + * return |
| 85 | + */ |
| 86 | + if (rdtsc() & 1) { |
| 87 | + return interrupted; |
| 88 | + } else { |
| 89 | + return 0; |
| 90 | + } |
| 91 | +} |
| 92 | + |
| 93 | +void *switch_back_to; |
| 94 | + |
| 95 | +void switch_back(int arg1, int arg2, int arg3) |
| 96 | +{ |
| 97 | + printf("Switching back (%d, %d, %d) sbt %xh\n", |
| 98 | + arg1, arg2, arg3, (int)(long)switch_back_to); |
| 99 | + xuk_switch(switch_back_to, &switch_back_to); |
| 100 | +} |
| 101 | + |
| 102 | +void test_switch(void) |
| 103 | +{ |
| 104 | + static unsigned long long stack[256]; |
| 105 | + long args[] = { 5, 4, 3 }; |
| 106 | + int eflags = 0x20; /* interrupts disabled */ |
| 107 | + |
| 108 | + long handle = xuk_setup_stack((long)(sizeof(stack) + (char *)stack), |
| 109 | + switch_back, eflags, args, 3); |
| 110 | + |
| 111 | + printf("Switching to %xh (stack %xh)\n", |
| 112 | + (int)handle, (int)(long)&stack[0]); |
| 113 | + __asm__ volatile("cli"); |
| 114 | + xuk_switch((void *)handle, &switch_back_to); |
| 115 | + __asm__ volatile("sti"); |
| 116 | + printf("Back from switch\n"); |
| 117 | +} |
| 118 | + |
| 119 | +void local_ipi_handler(void *arg, int err) |
| 120 | +{ |
| 121 | + printf("local IPI handler on CPU%d\n", (int)(long)xuk_get_f_ptr()); |
| 122 | +} |
| 123 | + |
| 124 | +/* Sends an IPI to the current CPU and validates it ran */ |
| 125 | +void test_local_ipi(void) |
| 126 | +{ |
| 127 | + printf("Testing a local IPI on CPU%d\n", (int)(long)xuk_get_f_ptr()); |
| 128 | + |
| 129 | + _apic.ICR_HI = (struct apic_icr_hi) {}; |
| 130 | + _apic.ICR_LO = (struct apic_icr_lo) { |
| 131 | + .delivery_mode = FIXED, |
| 132 | + .vector = 0x90, |
| 133 | + .shorthand = SELF, |
| 134 | + }; |
| 135 | +} |
| 136 | + |
| 137 | +void _cpu_start(int cpu) |
| 138 | +{ |
| 139 | + _putchar = putchar; |
| 140 | + printf("Entering demo kernel\n"); |
| 141 | + |
| 142 | + /* Make sure the FS/GS pointers work, then set F to store our |
| 143 | + * CPU ID |
| 144 | + */ |
| 145 | + xuk_set_f_ptr(cpu, (void *)(long)(0x19283700 + cpu)); |
| 146 | + xuk_set_g_ptr(cpu, (void *)(long)(0xabacad00 + cpu)); |
| 147 | + printf("fptr %p gptr %p\n", xuk_get_f_ptr(), xuk_get_g_ptr()); |
| 148 | + |
| 149 | + xuk_set_f_ptr(cpu, (void *)(long)cpu); |
| 150 | + |
| 151 | + /* Set up this CPU's timer */ |
| 152 | + /* FIXME: this sets up a separate vector for every CPU's |
| 153 | + * timer, and we'll run out. They should share the vector but |
| 154 | + * still have individually-set APIC config. Probably wants a |
| 155 | + * "timer" API |
| 156 | + */ |
| 157 | + xuk_set_isr(INT_APIC_LVT_TIMER, 10, handler_timer, 0); |
| 158 | + _apic.INIT_COUNT = 5000000; |
| 159 | + test_timers(); |
| 160 | + |
| 161 | + if (cpu == 0) { |
| 162 | + xuk_set_isr(0x1f3, 0, (void *)handler_f3, (void *)0x12345678); |
| 163 | + } |
| 164 | + |
| 165 | + __asm__ volatile("int $0xf3"); |
| 166 | + |
| 167 | + /* Fire it all up */ |
| 168 | + printf("Enabling Interrupts\n"); |
| 169 | + __asm__ volatile("sti"); |
| 170 | + printf("Interrupts are unmasked (eflags %xh), here we go...\n", |
| 171 | + eflags()); |
| 172 | + |
| 173 | + /* Wait a teeny bit then send an IPI to CPU0, which will hit |
| 174 | + * the unhandled_vector handler |
| 175 | + */ |
| 176 | + if (cpu == 1) { |
| 177 | + int t0 = rdtsc(); |
| 178 | + |
| 179 | + while (rdtsc() - t0 < 1000000) { |
| 180 | + } |
| 181 | + |
| 182 | + _apic.ICR_HI = (struct apic_icr_hi) { |
| 183 | + .destination = 0 |
| 184 | + }; |
| 185 | + _apic.ICR_LO = (struct apic_icr_lo) { |
| 186 | + .delivery_mode = FIXED, |
| 187 | + .vector = 66, |
| 188 | + }; |
| 189 | + while (_apic.ICR_LO.send_pending) { |
| 190 | + } |
| 191 | + } |
| 192 | + |
| 193 | + test_switch(); |
| 194 | + |
| 195 | + xuk_set_isr(XUK_INT_RAW_VECTOR(0x90), -1, local_ipi_handler, 0); |
| 196 | + test_local_ipi(); |
| 197 | + |
| 198 | + printf("CPU%d initialized, sleeping\n", cpu); |
| 199 | + while (1) { |
| 200 | + __asm__ volatile("hlt"); |
| 201 | + } |
| 202 | +} |
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