From c71af00da3d9d5dd5dd92abbc8f445cdcf989b1f Mon Sep 17 00:00:00 2001
From: 092vk <vk092kumar@gmail.com>
Date: Sun, 29 Jun 2025 08:42:19 +0530
Subject: [PATCH 1/2] made the verilog module consistent with the simulation
 logic

---
 src/simulator/src/sequential/DflipFlop.js | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/simulator/src/sequential/DflipFlop.js b/src/simulator/src/sequential/DflipFlop.js
index f21fe2a19..ff95e957b 100644
--- a/src/simulator/src/sequential/DflipFlop.js
+++ b/src/simulator/src/sequential/DflipFlop.js
@@ -135,13 +135,18 @@ export default class DflipFlop extends CircuitElement {
 module DflipFlop(q, q_inv, clk, d, a_rst, pre, en);
     parameter WIDTH = 1;
     output reg [WIDTH-1:0] q, q_inv;
-    input clk, a_rst, pre, en;
-    input [WIDTH-1:0] d;
+    input clk, a_rst, en;
+    input [WIDTH-1:0] d, pre;
 
     always @ (posedge clk or posedge a_rst)
     if (a_rst) begin
-        q <= 'b0;
-        q_inv <= 'b1;
+        if (^pre === 1'bx) begin
+            q <= {WIDTH{1'b0}};
+            q_inv <= {WIDTH{1'b1}};
+        end else begin
+            q <= pre;
+            q_inv <= ~pre;
+        end
     end else if (en == 0) ;
     else begin
         q <= d;

From ed503022d6dff4422f83b2a1e622bdc5c37d8206 Mon Sep 17 00:00:00 2001
From: 092vk <vk092kumar@gmail.com>
Date: Sun, 24 Aug 2025 11:18:41 +0530
Subject: [PATCH 2/2] fixed logic

---
 src/simulator/src/sequential/DflipFlop.js | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/src/simulator/src/sequential/DflipFlop.js b/src/simulator/src/sequential/DflipFlop.js
index ff95e957b..23f7213cb 100644
--- a/src/simulator/src/sequential/DflipFlop.js
+++ b/src/simulator/src/sequential/DflipFlop.js
@@ -138,19 +138,15 @@ module DflipFlop(q, q_inv, clk, d, a_rst, pre, en);
     input clk, a_rst, en;
     input [WIDTH-1:0] d, pre;
 
-    always @ (posedge clk or posedge a_rst)
-    if (a_rst) begin
-        if (^pre === 1'bx) begin
-            q <= {WIDTH{1'b0}};
-            q_inv <= {WIDTH{1'b1}};
-        end else begin
+    always @ (posedge clk or posedge a_rst) begin
+        if (a_rst) begin
             q <= pre;
             q_inv <= ~pre;
+        end else if (en) begin
+            q <= d;
+            q_inv <= ~d;
         end
-    end else if (en == 0) ;
-    else begin
-        q <= d;
-        q_inv <= ~d;
+        // When en == 0, hold current state
     end
 endmodule
     `