Feat: FIFO Queue Component

[Nihal4777]

The component implements a First-In-First-Out (FIFO) logic queue that can enqueue and dequeue bit-width-limited values on clock edges.

Characteristics:

• Supports ENQ (enqueue), DEQ (dequeue), and RST (reset) control signals.
• Operates on the rising edge of a CLK input.
• Maintains an internal buffer of configurable depth.
• Outputs:
  • Q: the value dequeued (only updates on DEQ).
  • EMP: High if the queue is empty.
  • FULL: High if the queue is full.