Debugging Gate Level Testing

[fkwilken]

Many people are running into issues while running gate level tests. Here are the most common fixes.

1. Test Time Out: if your test is hanging, add a section to force a timeout after a known time. For Example:

initial #100000 $error("Timeout");

2. Reset Signals - make sure you are actually using your reset. Reset should start high, go low, and then go back high.
3. Power Signals - make sure you are defining power rails AND CONNECTING THEM to your instantiation. You can use .* to autoconnect traces with the same name.

`ifdef USE_POWER_PINS
    wire VPWR;
    wire VGND;
    assign VPWR=1;
    assign VGND=0;
`endif

fib Fib (..., .*));

4. Timescale - make sure your design has a set timescale such as `timescale 1ns/1ps