Merge branch 'cheriot' into 20250625-cheriot_import_loadglobal

resistor · web-flow · commit 49f5b47d83df · 2025-07-13T16:38:22.000+07:00
diff --git a/clang/include/clang/Basic/DiagnosticGroups.td b/clang/include/clang/Basic/DiagnosticGroups.td
@@ -172,6 +172,9 @@ def CheriPedantic : DiagGroup<"cheri-pedantic", [CHERICapabilityToIntegerCast, C
 // Warnings/Errors for bugs in the MIPS/CHERI backend
 def MIPSCHERIBugs: DiagGroup<"mips-cheri-bugs">;
 
+// Generally useful CHERI errors
+def CHERIMissingCompartment: DiagGroup<"cheri-missing-compartment">;
+
 def C99Compat : DiagGroup<"c99-compat">;
 def C23Compat : DiagGroup<"c23-compat">;
 def : DiagGroup<"c2x-compat", [C23Compat]>;
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -157,8 +157,8 @@ def err_cheriot_invalid_sealed_declaration
     : Error<"cannot declare a sealed variable as %0">;
 def err_cheriot_invalid_sealing_key_type_name
     : Error<"the sealing key type name '%0' is not a valid identifier">;
-def err_cheriot_use_of_builtin_sealing_key_type_no_compartment
-    : Error<"%0 used, but no compartment name given">;
+def warn_cheriot_use_of_builtin_sealing_key_type_no_compartment
+    : Warning<"%0 used, but no compartment name given">,InGroup<CHERIMissingCompartment>,DefaultError;
 
 // C99 variable-length arrays
 def ext_vla : Extension<"variable length arrays are a C99 feature">,
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
@@ -306,9 +306,9 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
 
     // Macros for CHERIoT in the default and bare-metal ABIs.
     if (ABI == "cheriot" || ABI == "cheriot-baremetal")
-      Builder.defineMacro("__CHERIOT__", "20250610");
+      Builder.defineMacro("__CHERIOT__", "20250701");
     if (ABI == "cheriot-baremetal")
-      Builder.defineMacro("__CHERIOT_BAREMETAL__", "20250610");
+      Builder.defineMacro("__CHERIOT_BAREMETAL__", "20250701");
 
     Builder.defineMacro("__riscv_clen", Twine(getCHERICapabilityWidth()));
     // TODO: _MIPS_CAP_ALIGN_MASK equivalent?
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
@@ -2938,7 +2938,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID,
     }
     if (getLangOpts().CheriCompartmentName.empty()) {
       Diag(Arg->getExprLoc(),
-           diag::err_cheriot_use_of_builtin_sealing_key_type_no_compartment)
+           diag::warn_cheriot_use_of_builtin_sealing_key_type_no_compartment)
           << Context.BuiltinInfo.getName(
                  Builtin::BI__builtin_cheriot_sealing_type);
     }
diff --git a/clang/test/Preprocessor/init.c b/clang/test/Preprocessor/init.c
@@ -391,8 +391,8 @@
 // Check for CHERIoT-specific defines
 // RUN: %clang_cc1 %s -o - "-triple" "riscv32-unknown-unknown" "-mframe-pointer=none" "-mcmodel=small" "-target-cpu" "cheriot" "-target-feature" "+xcheri" "-target-feature" "-64bit" "-target-feature" "-relax" "-target-feature" "-xcheri-rvc" "-target-feature" "-save-restore" "-target-abi" "cheriot" -E -dM < /dev/null | FileCheck -check-prefix CHERIOT %s
 // RUN: %clang_cc1 %s -o - "-triple" "riscv32-unknown-unknown" "-mframe-pointer=none" "-mcmodel=small" "-target-cpu" "cheriot" "-target-feature" "+xcheri" "-target-feature" "-64bit" "-target-feature" "-relax" "-target-feature" "-xcheri-rvc" "-target-feature" "-save-restore" "-target-abi" "cheriot-baremetal" -E -dM < /dev/null | FileCheck -check-prefixes CHERIOT,CHERIOT-BAREMETAL %s
-// CHERIOT-BAREMETAL: #define __CHERIOT_BAREMETAL__ 20250610
-// CHERIOT: #define __CHERIOT__ 20250610
+// CHERIOT-BAREMETAL: #define __CHERIOT_BAREMETAL__ 20250701
+// CHERIOT: #define __CHERIOT__ 20250701
 
 
 // RUN: %cheri128_cc1 -fgnuc-version=4.2.1 -E -dM -ffreestanding < /dev/null | FileCheck -check-prefixes CHERI-COMMON,CHERI-MIPS,CHERI128 %s
diff --git a/lldb/include/lldb/lldb-enumerations.h b/lldb/include/lldb/lldb-enumerations.h
@@ -195,11 +195,12 @@ enum Format {
                          ///< character arrays that can contain non printable
                          ///< characters
   eFormatAddressInfo,    ///< Describe what an address points to (func + offset
-                      ///< with file/line, symbol + offset, data, etc)
-  eFormatHexFloat,    ///< ISO C99 hex float string
-  eFormatInstruction, ///< Disassemble an opcode
-  eFormatVoid,        ///< Do not print this
+                         ///< with file/line, symbol + offset, data, etc)
+  eFormatHexFloat,       ///< ISO C99 hex float string
+  eFormatInstruction,    ///< Disassemble an opcode
+  eFormatVoid,           ///< Do not print this
   eFormatUnicode8,
+  eFormatCheriotCapability,
   kNumFormats
 };
 
diff --git a/lldb/source/Commands/CommandObjectMemory.cpp b/lldb/source/Commands/CommandObjectMemory.cpp
@@ -1354,6 +1354,7 @@ class CommandObjectMemoryWrite : public CommandObjectParsed {
       case eFormatAddressInfo:
       case eFormatHexFloat:
       case eFormatInstruction:
+      case eFormatCheriotCapability:
       case eFormatVoid:
         result.AppendError("unsupported format for writing memory");
         return;
diff --git a/lldb/source/Core/DumpDataExtractor.cpp b/lldb/source/Core/DumpDataExtractor.cpp
@@ -413,6 +413,116 @@ lldb::offset_t lldb_private::DumpDataExtractor(
     }
 
     switch (item_format) {
+    case eFormatCheriotCapability: {
+      if (item_byte_size != 8) {
+        s->Printf("error: unsupported byte size (%" PRIu64
+                  ") for cheriot capability format",
+                  (uint64_t)item_byte_size);
+        return offset;
+      }
+
+      // Extract the raw bits of the capability.
+      uint64_t uval64 = DE.GetMaxU64(&offset, item_byte_size);
+      uint32_t addr = uval64;
+      uint32_t meta = (uval64 >> 32);
+      unsigned B = meta & 0x1FF;
+      unsigned T = (meta >> 9) & 0x1FF;
+      unsigned E = (meta >> 18) & 0xF;
+      unsigned otype = (meta >> 22) & 0x7;
+      std::bitset<6> perms = (meta >> 25) & 0x3F;
+
+      bool GL = perms[5];
+      bool LD = false;
+      bool MC = false;
+      bool SD = false;
+      bool SL = false;
+      bool LM = false;
+      bool LG = false;
+      bool SR = false;
+      bool EX = false;
+      bool U0 = false;
+      bool SE = false;
+      bool US = false;
+
+      // Cheriot capabilities pack 11 permissions into 6 bits,
+      // so decoding is non-trivial.
+      if (perms[4] && perms[3]) {
+        LD = MC = SD = true;
+        SL = perms[2];
+        LM = perms[1];
+        LD = perms[0];
+      } else if (perms[4] && !perms[3] && perms[2]) {
+        LD = MC = true;
+        LM = perms[1];
+        LG = perms[0];
+      } else if (perms[4] && !perms[3] && !perms[2] && !perms[1] && !perms[0]) {
+        SD = MC = true;
+      } else if (perms[4] && !perms[3] && !perms[2]) {
+        LD = perms[1];
+        SD = perms[0];
+      } else if (!perms[4] && perms[3]) {
+        EX = LD = MC = true;
+        SR = perms[2];
+        LM = perms[1];
+        LG = perms[0];
+      } else {
+        U0 = perms[2];
+        SE = perms[1];
+        US = perms[0];
+      }
+
+      // Render the permissions to a string.
+      std::string perm_string;
+      perm_string += GL ? 'G' : '-';
+      perm_string += ' ';
+      perm_string += LD ? 'R' : '-';
+      perm_string += SD ? 'W' : '-';
+      perm_string += MC ? 'c' : '-';
+      perm_string += LG ? 'g' : '-';
+      perm_string += LM ? 'm' : '-';
+      perm_string += SL ? 'l' : '-';
+      perm_string += ' ';
+      perm_string += EX ? 'X' : '-';
+      perm_string += SR ? 'a' : '-';
+      perm_string += ' ';
+      perm_string += SE ? 'S' : '-';
+      perm_string += US ? 'U' : '-';
+      perm_string += U0 ? '0' : '-';
+
+      // Decode otype, and present with a semantic string if possible.
+      if (otype != 0 && !EX)
+        otype += 8;
+      constexpr llvm::StringRef otypes[] = {
+          "[unsealed]",
+          "[IRQ inherit forward sentry]",
+          "[IRQ disable forward sentry]",
+          "[IRQ enable forward sentry]",
+          "[IRQ disable return sentry]",
+          "[IRQ enable return sentry]",
+      };
+      llvm::StringRef otype_str = (otype < sizeof(otypes)) ? otypes[otype] : "";
+
+      // Compute the base and top addresses for the bounds.
+      unsigned e = (E != 15) ? E : 24;
+      uint64_t a_top = addr >> (e + 9);
+      uint64_t a_mid = (addr >> e) & 0x1FF;
+      uint64_t a_hi = (a_mid < B) ? 1 : 0;
+      uint64_t t_hi = (T < B) ? 1 : 0;
+      uint64_t c_b = -a_hi;
+      uint64_t c_t = t_hi - a_hi;
+      uint64_t a_top_base = a_top + c_b;
+      uint64_t a_top_top = a_top + c_t;
+      uint64_t base = ((a_top_base << 9) + B) << e;
+      uint64_t top = ((a_top_top << 9) + T) << e;
+      uint64_t len = top - base;
+
+      s->Printf("0x%08" PRIx32 " (v:? 0x%08" PRIx64 "-0x%08" PRIx64
+                " l:0x%" PRIx64 " o:0x%x%s p: %s)",
+                addr, base, top, len, otype, otype_str.data(),
+                perm_string.c_str());
+
+      break;
+    }
     case eFormatBoolean:
       if (item_byte_size <= 8)
         s->Printf("%s", DE.GetMaxU64Bitfield(&offset, item_byte_size,
diff --git a/lldb/source/DataFormatters/FormatManager.cpp b/lldb/source/DataFormatters/FormatManager.cpp
@@ -72,6 +72,7 @@ static constexpr FormatInfo g_format_infos[] = {
     {eFormatInstruction, 'i', "instruction"},
     {eFormatVoid, 'v', "void"},
     {eFormatUnicode8, 'u', "unicode8"},
+    {eFormatCheriotCapability, 'P', "cheriot capability"},
 };
 
 static_assert((sizeof(g_format_infos) / sizeof(g_format_infos[0])) ==
diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -4743,6 +4743,10 @@ bool ParseRegisters(
                   "format and encoding for gdb type %s",
                   gdb_type.c_str());
             }
+
+            if (gdb_type == "cheriot capability") {
+              reg_info.format = eFormatCheriotCapability;
+            }
           }
         }
 
diff --git a/lldb/unittests/Core/DumpDataExtractorTest.cpp b/lldb/unittests/Core/DumpDataExtractorTest.cpp
@@ -272,6 +272,11 @@ TEST_F(DumpDataExtractorTest, Formats) {
 
   // Has no special handling, intended for use elsewhere.
   TestDump<int>(99, lldb::Format::eFormatVoid, "0x00000063");
+
+  // Cheriot capability formatting
+  TestDump<uint64_t>(0x7608d4cd00220b34, lldb::eFormatCheriotCapability,
+                     "0x00220b34 (v:? 0x00220b34-0x002211a8 l:0x674 "
+                     "o:0x0[unsealed] p: G RWc-m- -- ---)");
 }
 
 TEST_F(DumpDataExtractorTest, FormatCharArray) {
@@ -403,4 +408,9 @@ TEST_F(DumpDataExtractorTest, ItemByteSizeErrors) {
   TestDumpWithItemByteSize(
       17, lldb::Format::eFormatHexFloat,
       "error: unsupported byte size (17) for hex float format");
+
+  // Cheriot capabilities must be 8 bytes.
+  TestDumpWithItemByteSize(
+      17, lldb::Format::eFormatCheriotCapability,
+      "error: unsupported byte size (17) for cheriot capability format");
 }
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -787,6 +787,8 @@ class TargetTransformInfo {
   AddressingModeKind getPreferredAddressingMode(const Loop *L,
                                                 ScalarEvolution *SE) const;
 
+  bool isLegalBaseRegForLSR(const SCEV *) const;
+
   /// Return true if the target supports masked store.
   bool isLegalMaskedStore(Type *DataType, Align Alignment) const;
   /// Return true if the target supports masked load.
@@ -1996,6 +1998,7 @@ class TargetTransformInfo::Concept {
                           TargetLibraryInfo *LibInfo) = 0;
   virtual AddressingModeKind
     getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const = 0;
+  virtual bool isLegalBaseRegForLSR(const SCEV *) const = 0;
   virtual bool isLegalMaskedStore(Type *DataType, Align Alignment) = 0;
   virtual bool isLegalMaskedLoad(Type *DataType, Align Alignment) = 0;
   virtual bool isLegalNTStore(Type *DataType, Align Alignment) = 0;
@@ -2534,6 +2537,9 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
                                ScalarEvolution *SE) const override {
     return Impl.getPreferredAddressingMode(L, SE);
   }
+  bool isLegalBaseRegForLSR(const SCEV *S) const override {
+    return Impl.isLegalBaseRegForLSR(S);
+  }
   bool isLegalMaskedStore(Type *DataType, Align Alignment) override {
     return Impl.isLegalMaskedStore(DataType, Alignment);
   }
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -276,6 +276,8 @@ class TargetTransformInfoImplBase {
     return TTI::AMK_None;
   }
 
+  bool isLegalBaseRegForLSR(const SCEV *S) const { return true; }
+
   bool isLegalMaskedStore(Type *DataType, Align Alignment) const {
     return false;
   }
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -6296,12 +6296,6 @@ const SCEV *ScalarEvolution::createNodeForGEP(GEPOperator *GEP) {
   assert(GEP->getSourceElementType()->isSized() &&
          "GEP source element type must be sized");
 
-  const DataLayout &DL = F.getParent()->getDataLayout();
-  // FIXME: Ideally, we should teach Scalar Evolution to
-  // understand fat pointers.
-  if (DL.isFatPointer(GEP->getPointerOperandType()->getPointerAddressSpace()))
-    return getUnknown(GEP);
-
   SmallVector<const SCEV *, 4> IndexExprs;
   for (Value *Index : GEP->indices())
     IndexExprs.push_back(getSCEV(Index));
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -463,6 +463,10 @@ TargetTransformInfo::getPreferredAddressingMode(const Loop *L,
   return TTIImpl->getPreferredAddressingMode(L, SE);
 }
 
+bool TargetTransformInfo::isLegalBaseRegForLSR(const SCEV *S) const {
+  return TTIImpl->isLegalBaseRegForLSR(S);
+}
+
 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType,
                                              Align Alignment) const {
   return TTIImpl->isLegalMaskedStore(DataType, Alignment);
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -742,10 +742,10 @@ void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) {
           /*IsImport*/ false);
       auto Sym = C.getOrCreateSymbol(ExportName);
       OutStreamer->emitSymbolAttribute(Sym, MCSA_ELF_TypeObject);
-      // If the function isn't global, don't make its export table entry
-      // global either.  Two different compilation units in the same
-      // compartment may export different static things.
-      if (Entry.Fn.hasExternalLinkage() && !Entry.forceLocal)
+      // If the function isn't global, don't make its export table entry global
+      // either.  Two different compilation units in the same compartment may
+      // export different static things.
+      if (!Entry.Fn.isDiscardableIfUnused() && !Entry.forceLocal)
         OutStreamer->emitSymbolAttribute(Sym, MCSA_Global);
       OutStreamer->emitValueToAlignment(Align(4));
       OutStreamer->emitLabel(Sym);
@@ -771,7 +771,7 @@ void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) {
         // Emit symbol alias in the export table for the alias using the same
         // attributes, linkage, and size as the primary entry.
         OutStreamer->emitSymbolAttribute(AliasExportSym, MCSA_ELF_TypeObject);
-        if (GA->hasExternalLinkage() && !Entry.forceLocal)
+        if (!GA->isDiscardableIfUnused() && !Entry.forceLocal)
           OutStreamer->emitSymbolAttribute(AliasExportSym, MCSA_Global);
         OutStreamer->emitAssignment(AliasExportSym,
                                     MCSymbolRefExpr::create(Sym, C));
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -263,6 +263,10 @@ def simm12 : RISCVSImmLeafOp<12> {
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
       return isInt<12>(Imm);
+    // Needed to make CHERIOT mnemonic aliases work.
+    if (STI.hasFeature(RISCV::FeatureVendorXCheriot) &&
+        MCOp.isExpr())
+      return true;
     return MCOp.isBareSymbolRef();
   }];
 }
@@ -292,6 +296,10 @@ class UImm20OperandMaybeSym : RISCVUImmOp<20> {
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
       return isUInt<20>(Imm);
+    // Needed to make CHERIOT mnemonic aliases work.
+    if (STI.hasFeature(RISCV::FeatureVendorXCheriot) &&
+        MCOp.isExpr())
+      return true;
     return MCOp.isBareSymbolRef();
   }];
 }
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td
@@ -2056,9 +2056,8 @@ def PseudoCTAIL : Pseudo<(outs), (ins cap_call_symbol:$dst), []> {
   let AsmString = "ctail\t$dst";
 }
 
-let Predicates = [HasCheriot] in def : InstAlias<
-                                           "ct.ctail $dst",
-                                           (PseudoCTAIL cap_call_symbol:$dst)>;
+let Predicates = [HasCheriot] in
+def : InstAlias<"ct.ctail $dst", (PseudoCTAIL cap_call_symbol:$dst)>;
 
 let Predicates = [HasCheri, IsCapMode, IsPureCapABI],
     isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [C2] in
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -9,6 +9,7 @@
 #include "RISCVTargetTransformInfo.h"
 #include "MCTargetDesc/RISCVMatInt.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/Analysis/ScalarEvolution.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/CodeGen/BasicTTIImpl.h"
 #include "llvm/CodeGen/CostTable.h"
@@ -2401,6 +2402,26 @@ RISCVTTIImpl::getPreferredAddressingMode(const Loop *L,
   return BasicTTIImplBase::getPreferredAddressingMode(L, SE);
 }
 
+bool RISCVTTIImpl::isLegalBaseRegForLSR(const SCEV *S) const {
+  if (ST->hasVendorXCheriot()) {
+    // Disallow any add-recurrence SCEV where the base offset is negative.
+    // This is needed because CHERIoT can't represent pointers before the
+    // beginning of an array.
+    if (const auto *AddRec = dyn_cast<SCEVAddRecExpr>(S)) {
+      const auto *StartAdd = dyn_cast<SCEVAddExpr>(AddRec->getStart());
+      if (StartAdd) {
+        const auto *Offset = dyn_cast<SCEVConstant>(StartAdd->getOperand(0));
+        if (Offset && Offset->getValue()->isNegative())
+          return false;
+        Offset = dyn_cast<SCEVConstant>(StartAdd->getOperand(1));
+        if (Offset && Offset->getValue()->isNegative())
+          return false;
+      }
+    }
+  }
+  return BasicTTIImplBase::isLegalBaseRegForLSR(S);
+}
+
 bool RISCVTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
                                  const TargetTransformInfo::LSRCost &C2) {
   // RISC-V specific here are "instruction number 1st priority".
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -394,6 +394,8 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
   TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L,
                                                      ScalarEvolution *SE) const;
 
+  bool isLegalBaseRegForLSR(const SCEV *S) const;
+
   unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
     if (Vector)
       return RISCVRegisterClass::VRRC;
diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
diff --git a/llvm/test/CodeGen/RISCV/cheri/calling-conv-il32pc64.ll b/llvm/test/CodeGen/RISCV/cheri/calling-conv-il32pc64.ll
diff --git a/llvm/test/CodeGen/RISCV/cheri/calling-conv-l64pc128.ll b/llvm/test/CodeGen/RISCV/cheri/calling-conv-l64pc128.ll
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-global-weak.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-global-weak.ll
diff --git a/llvm/test/MC/RISCV/cheri/cheriot-only.s b/llvm/test/MC/RISCV/cheri/cheriot-only.s
diff --git a/llvm/test/MC/RISCV/cheri/cheriot.s b/llvm/test/MC/RISCV/cheri/cheriot.s
diff --git a/llvm/test/Transforms/LoopIdiom/cheri-preserve-tags-memcpy.ll b/llvm/test/Transforms/LoopIdiom/cheri-preserve-tags-memcpy.ll
diff --git a/llvm/test/Transforms/LoopIdiom/cheri-preserve-tags-store.ll b/llvm/test/Transforms/LoopIdiom/cheri-preserve-tags-store.ll
diff --git a/llvm/test/Transforms/LoopStrengthReduce/cheriot-strlen.ll b/llvm/test/Transforms/LoopStrengthReduce/cheriot-strlen.ll

Original file line number	Diff line number	Diff line change
`@@ -2938,7 +2938,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID,`
`2938`	`2938`	`}`
`2939`	`2939`	`if (getLangOpts().CheriCompartmentName.empty()) {`
`2940`	`2940`	`Diag(Arg->getExprLoc(),`
`2941`		`- diag::err_cheriot_use_of_builtin_sealing_key_type_no_compartment)`
	`2941`	`+ diag::warn_cheriot_use_of_builtin_sealing_key_type_no_compartment)`
`2942`	`2942`	`<< Context.BuiltinInfo.getName(`
`2943`	`2943`	`Builtin::BI__builtin_cheriot_sealing_type);`
`2944`	`2944`	`}`
Original file line number	Diff line number	Diff line change
`@@ -4743,6 +4743,10 @@ bool ParseRegisters(`
`4743`	`4743`	`"format and encoding for gdb type %s",`
`4744`	`4744`	`gdb_type.c_str());`
`4745`	`4745`	`}`
	`4746`	`+`
	`4747`	`+ if (gdb_type == "cheriot capability") {`
	`4748`	`+ reg_info.format = eFormatCheriotCapability;`
	`4749`	`+ }`
`4746`	`4750`	`}`
`4747`	`4751`	`}`
`4748`	`4752`