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johnydhuangjohnydhuang
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otp: fix otp_info for ast_10xx
Fix otp_info for ast_10xx Signed-off-by: Johnny Huang <[email protected]> Change-Id: Ia4eb569f7d519cc7135a150dbf9adc2fac95260c
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‎drivers/otp/otp_info_10xx.h

Lines changed: 17 additions & 102 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
* Do not edit it.
44
*/
55

6-
#define OTP_INFO_VER "2.0.0"
6+
#define OTP_INFO_VER "2.0.1"
77
#define OTP_REG_RESERVED -1
88
#define OTP_REG_VALUE -2
99
#define OTP_REG_VALID_BIT -3
@@ -32,84 +32,22 @@ struct scu_info {
3232
static const struct otpstrap_info ast1030a0_strap_info[] = {
3333
{ 0, 1, 0, "Disable Secure Boot" },
3434
{ 0, 1, 1, "Enable Secure Boot" },
35-
{ 1, 1, 0, "Disable boot from eMMC" },
36-
{ 1, 1, 1, "Enable boot from eMMC" },
37-
{ 2, 1, 0, "Disable Boot from debug SPI" },
38-
{ 2, 1, 1, "Enable Boot from debug SPI" },
39-
{ 3, 1, 0, "Enable ARM CM3" },
40-
{ 3, 1, 1, "Disable ARM CM3" },
41-
{ 4, 1, 0, "No VGA BIOS ROM, VGA BIOS is merged in the system BIOS" },
42-
{ 4, 1, 1, "Enable dedicated VGA BIOS ROM" },
43-
{ 5, 1, 0, "MAC 1 : RMII/NCSI" },
44-
{ 5, 1, 1, "MAC 1 : RGMII" },
45-
{ 6, 1, 0, "MAC 2 : RMII/NCSI" },
46-
{ 6, 1, 1, "MAC 2 : RGMII" },
47-
{ 7, 3, 0, "CPU Frequency : 1.2GHz" },
48-
{ 7, 3, 1, "CPU Frequency : 1.6GHz" },
49-
{ 7, 3, 2, "CPU Frequency : 1.2GHz" },
50-
{ 7, 3, 3, "CPU Frequency : 1.6GHz" },
51-
{ 7, 3, 4, "CPU Frequency : 800MHz" },
52-
{ 7, 3, 5, "CPU Frequency : 800MHz" },
53-
{ 7, 3, 6, "CPU Frequency : 800MHz" },
54-
{ 7, 3, 7, "CPU Frequency : 800MHz" },
55-
{ 10, 2, 0, "HCLK ratio AXI:AHB = default" },
56-
{ 10, 2, 1, "HCLK ratio AXI:AHB = 2:1" },
57-
{ 10, 2, 2, "HCLK ratio AXI:AHB = 3:1" },
58-
{ 10, 2, 3, "HCLK ratio AXI:AHB = 4:1" },
59-
{ 12, 2, 0, "VGA memory size : 8MB" },
60-
{ 12, 2, 1, "VGA memory size : 16MB" },
61-
{ 12, 2, 2, "VGA memory size : 32MB" },
62-
{ 12, 2, 3, "VGA memory size : 64MB" },
63-
{ 15, 1, 0, "CPU/AXI clock ratio : 2:1" },
64-
{ 15, 1, 1, "CPU/AXI clock ratio : 1:1" },
35+
{ 1, 2, OTP_REG_RESERVED, "Reserved" },
36+
{ 3, 1, 0, "Address offset of single chip ABR mode : 1/2" },
37+
{ 3, 1, 1, "Address offset of single chip ABR mode : 1/3" },
38+
{ 4, 13, OTP_REG_RESERVED, "Reserved" },
6539
{ 16, 1, 0, "Enable ARM JTAG debug" },
6640
{ 16, 1, 1, "Disable ARM JTAG debug" },
67-
{ 17, 1, 0, "VGA class code : vga_device" },
68-
{ 17, 1, 1, "VGA class code : video_device" },
69-
{ 18, 1, 0, "Enable debug interfaces 0" },
70-
{ 18, 1, 1, "Disable debug interfaces 0" },
71-
{ 19, 1, 0, "Boot from eMMC speed mode : normal" },
72-
{ 19, 1, 1, "Boot from eMMC speed mode : high" },
73-
{ 20, 1, 0, "Disable Pcie EHCI device" },
74-
{ 20, 1, 1, "Enable Pcie EHCI device" },
75-
{ 21, 1, 0, "Enable ARM JTAG trust world debug" },
76-
{ 21, 1, 1, "Disable ARM JTAG trust world debug" },
77-
{ 22, 1, 0, "Normal BMC mode" },
78-
{ 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" },
79-
{ 23, 1, 0, "SSPRST# pin is for secondary processor dedicated reset pin" },
80-
{ 23, 1, 1, "SSPRST# pin is for PCIE root complex dedicated reset pin" },
81-
{ 24, 1, 0, "Enable watchdog to reset full chip" },
82-
{ 24, 1, 1, "Disable watchdog to reset full chip" },
83-
{ 25, 2, 0, "Internal bridge speed selection : 1x" },
84-
{ 25, 2, 1, "Internal bridge speed selection : 1/2x" },
85-
{ 25, 2, 2, "Internal bridge speed selection : 1/4x" },
86-
{ 25, 2, 3, "Internal bridge speed selection : 1/8x" },
87-
{ 29, 1, 0, "Enable RVAS function" },
88-
{ 29, 1, 1, "Disable RVAS function" },
89-
{ 32, 1, 0, "MAC 3 : RMII/NCSI" },
90-
{ 32, 1, 1, "MAC 3 : RGMII" },
91-
{ 33, 1, 0, "MAC 4 : RMII/NCSI" },
92-
{ 33, 1, 1, "MAC 4 : RGMII" },
93-
{ 34, 1, 0, "SuperIO configuration address : 0x2e" },
94-
{ 34, 1, 1, "SuperIO configuration address : 0x4e" },
95-
{ 35, 1, 0, "Enable LPC to decode SuperIO" },
96-
{ 35, 1, 1, "Disable LPC to decode SuperIO" },
97-
{ 36, 1, 0, "Enable debug interfaces 1" },
98-
{ 36, 1, 1, "Disable debug interfaces 1" },
99-
{ 37, 1, 0, "Disable ACPI function" },
100-
{ 37, 1, 1, "Enable ACPI function" },
101-
{ 38, 1, 0, "Select LPC/eSPI : eSPI" },
102-
{ 38, 1, 1, "Select LPC/eSPI : LPC" },
103-
{ 39, 1, 0, "Disable SAFS mode" },
104-
{ 39, 1, 1, "Enable SAFS mode" },
41+
{ 18, 14, OTP_REG_RESERVED, "Reserved" },
42+
{ 32, 4, OTP_REG_RESERVED, "Reserved" },
43+
{ 36, 1, 0, "Enable debug interfaces" },
44+
{ 36, 1, 1, "Disable debug interfaces" },
45+
{ 37, 3, OTP_REG_RESERVED, "Reserved" },
10546
{ 40, 1, 0, "Disable boot from uart5" },
10647
{ 40, 1, 1, "Enable boot from uart5" },
107-
{ 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" },
108-
{ 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" },
109-
{ 42, 1, 0, "Disable boot SPI 3B/4B address mode auto detection" },
110-
{ 42, 1, 1, "Enable boot SPI 3B/4B address mode auto detection" },
111-
{ 43, 1, 0, "Disable boot SPI or eMMC ABR" },
112-
{ 43, 1, 1, "Enable boot SPI or eMMC ABR" },
48+
{ 41, 2, OTP_REG_RESERVED, "Reserved" },
49+
{ 43, 1, 0, "Disable boot SPI ABR" },
50+
{ 43, 1, 1, "Enable boot SPI ABR" },
11351
{ 44, 1, 0, "Boot SPI ABR Mode : dual" },
11452
{ 44, 1, 1, "Boot SPI ABR Mode : single" },
11553
{ 45, 3, 0, "Boot SPI flash size : 0MB" },
@@ -120,36 +58,13 @@ static const struct otpstrap_info ast1030a0_strap_info[] = {
12058
{ 45, 3, 5, "Boot SPI flash size : 32MB" },
12159
{ 45, 3, 6, "Boot SPI flash size : 64MB" },
12260
{ 45, 3, 7, "Boot SPI flash size : 128MB" },
123-
{ 48, 1, 0, "Disable host SPI ABR" },
124-
{ 48, 1, 1, "Enable host SPI ABR" },
125-
{ 49, 1, 0, "Disable host SPI ABR mode select pin" },
126-
{ 49, 1, 1, "Enable host SPI ABR mode select pin" },
127-
{ 50, 1, 0, "Host SPI ABR mode : dual" },
128-
{ 50, 1, 1, "Host SPI ABR mode : single" },
129-
{ 51, 3, 0, "Host SPI flash size : 0MB" },
130-
{ 51, 3, 1, "Host SPI flash size : 2MB" },
131-
{ 51, 3, 2, "Host SPI flash size : 4MB" },
132-
{ 51, 3, 3, "Host SPI flash size : 8MB" },
133-
{ 51, 3, 4, "Host SPI flash size : 16MB" },
134-
{ 51, 3, 5, "Host SPI flash size : 32MB" },
135-
{ 51, 3, 6, "Host SPI flash size : 64MB" },
136-
{ 51, 3, 7, "Host SPI flash size : 128MB" },
61+
{ 48, 6, OTP_REG_RESERVED, "Reserved" },
13762
{ 54, 1, 0, "Disable boot SPI auxiliary control pins" },
13863
{ 54, 1, 1, "Enable boot SPI auxiliary control pins" },
139-
{ 55, 2, 0, "Boot SPI CRTM size : 0KB" },
140-
{ 55, 2, 1, "Boot SPI CRTM size : 256KB" },
141-
{ 55, 2, 2, "Boot SPI CRTM size : 512KB" },
142-
{ 55, 2, 3, "Boot SPI CRTM size : 1024KB" },
143-
{ 57, 2, 0, "Host SPI CRTM size : 0KB" },
144-
{ 57, 2, 1, "Host SPI CRTM size : 1024KB" },
145-
{ 57, 2, 2, "Host SPI CRTM size : 2048KB" },
146-
{ 57, 2, 3, "Host SPI CRTM size : 4096KB" },
147-
{ 59, 1, 0, "Disable host SPI auxiliary control pins" },
148-
{ 59, 1, 1, "Enable host SPI auxiliary control pins" },
149-
{ 60, 1, 0, "Disable GPIO pass through" },
150-
{ 60, 1, 1, "Enable GPIO pass through" },
64+
{ 57, 7, OTP_REG_RESERVED, "Reserved" },
15165
{ 62, 1, 0, "Disable dedicate GPIO strap pins" },
152-
{ 62, 1, 1, "Enable dedicate GPIO strap pins" }
66+
{ 62, 1, 1, "Enable dedicate GPIO strap pins" },
67+
{ 63, 1, OTP_REG_RESERVED, "Reserved" }
15368
};
15469

15570
static const struct otpconf_info ast1030a0_conf_info[] = {

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