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prepare documents for 2024Q3 release (#279)
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‎aadwarf32/aadwarf32.rst‎

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Copyright (c) 2003-2007, 2012, 2018, 2020-2023, Arm Limited and its affiliates. All rights reserved.
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Copyright (c) 2003-2007, 2012, 2018, 2020-2024, Arm Limited and its affiliates. All rights reserved.
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CC-BY-SA-4.0 AND Apache-Patent-License
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See LICENSE file for details
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‎aadwarf64-morello/aadwarf64-morello.rst‎

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Copyright (c) 2020-2023, Arm Limited and its affiliates. All rights reserved.
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Copyright (c) 2020-2024, Arm Limited and its affiliates. All rights reserved.
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CC-BY-SA-4.0 AND Apache-Patent-License
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‎aadwarf64/aadwarf64.rst‎

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Copyright (c) 2010, 2013, 2018, 2020-2023, Arm Limited and its affiliates. All rights reserved.
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Copyright (c) 2010, 2013, 2018, 2020-2024, Arm Limited and its affiliates. All rights reserved.
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CC-BY-SA-4.0 AND Apache-Patent-License
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| 2022Q3 | 20\ :sup:`th` October 2022 | - Added `Changes in vector length`_ at |
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| | | **Alpha** quality. |
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+--------+-----------------------------+----------------------------------------+
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| 2024Q3 | 5\ :sup:`th` September 2024 | In `DWARF register names_` and |
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| | | `Call frame instructions`_, add Dwarf |
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| | | support for unwinding with |
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| | | FEAT_PAuth_LR enabled. |
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+--------+-----------------------------+----------------------------------------+
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References

‎aaelf32/aaelf32.rst‎

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Copyright (c) 2005-2009, 2012, 2015, 2018, 2020-2023, Arm Limited and its affiliates. All rights
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Copyright (c) 2005-2009, 2012, 2015, 2018, 2020-2024, Arm Limited and its affiliates. All rights
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reserved. CC-BY-SA-4.0 AND Apache-Patent-License See LICENSE file
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for details
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affiliates. All rights reserved.
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.. |armarmv5_link| replace:: https://developer.arm.com/docs/ddi0100/latest/armv5-architecture-reference-manual

‎aaelf64-morello/aaelf64-morello.rst‎

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Copyright (c) 2020-2024, Arm Limited and its affiliates. All rights reserved.
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CC-BY-SA-4.0 AND Apache-Patent-License
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‎aaelf64/aaelf64.rst‎

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Copyright (c) 2011, 2013, 2018-2023, Arm Limited and its affiliates. All rights reserved.
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Copyright (c) 2011, 2013, 2018-2024, Arm Limited and its affiliates. All rights reserved.
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CC-BY-SA-4.0 AND Apache-Patent-License
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| | | - In `Program Loading`_, Relax BTI PLT |
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| | | requirement |
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+---------------+--------------------+-----------------------------------------+
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| 2023Q4 | 24\ :sup:`th` | - In `Program Property`_, |
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| | October 2023 | `Program Loading`_ and |
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| | | `Dynamic Linking`. Move description to|
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| | | `SYSVABI64`_ |
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+---------------+--------------------+-----------------------------------------+
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| 2024Q1 | 18\ :sup: `th` | - Move relocation codes from |
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| | March 2024 | `PAUTHABIELF64`_ into reserved space |
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| 2024Q3 | 5\ :sup:`th` | - In `Program Property`_, |
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| | September 2024 | `Program Loading`_, and |
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| | | `Dynamic Linking`_, move description |
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| | | to `SYSVABI64`_. |
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| | | - Move relocation codes from |
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| | | `PAUTHABIELF64`_ into reserved space. |
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| | | - Clarify use of addends in MOVZ, MOVK, |
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| | | and ADRP |
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+---------------+--------------------+-----------------------------------------+
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‎aapcs32/aapcs32.rst‎

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Copyright (c) 2003, 2005-2009, 2012, 2015, 2018, 2020-2023, Arm Limited and its affiliates. All rights reserved.
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Copyright (c) 2003, 2005-2009, 2012, 2015, 2018, 2020-2024, Arm Limited and its affiliates. All rights reserved.
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CC-BY-SA-4.0 AND Apache-Patent-License
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See LICENSE file for details
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.. |footer| replace:: Copyright © |copyright-date|, Arm Limited and its
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‎aapcs64-morello/aapcs64-morello.rst‎

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Copyright (c) 2020-2023, Arm Limited and its affiliates. All rights reserved.
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Copyright (c) 2020-2024, Arm Limited and its affiliates. All rights reserved.
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‎aapcs64/aapcs64.rst‎

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Copyright (c) 2011, 2013, 2018, 2020-2023, Arm Limited and its affiliates. All rights reserved.
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Copyright (c) 2011, 2013, 2018, 2020-2024, Arm Limited and its affiliates. All rights reserved.
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| 2023Q3 | 6\ :sup:`th` | In `Data Types`_ include _BitInt(N) in language mapping. |
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| | October 2023 | |
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+------------+--------------------+------------------------------------------------------------------+
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| 2024Q2 | 18\ :sup:'th' | - Change the status of the SME support from Alpha to Beta. |
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| | June 2024 | - Add soft-float PCS variant. |
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| 2024Q3 | 5\ :sup:`th` | - Change the status of the SME support from Alpha to Beta. |
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| | September 2024 | - Add soft-float PCS variant. |
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| | | - Add the __arm_get_current_vg SME support routine. |
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| | | - Clarify use of it when preserving z and p registers. |
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| | | - Clarify use of `it` when preserving z and p registers. |
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+------------+--------------------+------------------------------------------------------------------+
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‎addenda32/addenda32.rst‎

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Copyright (c) 2005-2009, 2012, 2015, 2018, 2020-2023, Arm Limited and its affiliates. All rights reserved.
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Copyright (c) 2005-2009, 2012, 2015, 2018, 2020-2024, Arm Limited and its affiliates. All rights reserved.
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CC-BY-SA-4.0 AND Apache-Patent-License
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