CMSIS 5.1.0 online documentation

Author: JonatanAntoni

README.md

@@ -1,6 +1,6 @@
 # CMSIS Version 5
 
-The branch *master* of this GitHub repository contains the CMSIS Version 5.0.1.  The [documentation](http://arm-software.github.io/CMSIS_5/General/html/index.html) is available under http://arm-software.github.io/CMSIS_5/General/html/index.html
+The branch *master* of this GitHub repository contains the CMSIS Version 5.1.0.  The [documentation](http://arm-software.github.io/CMSIS_5/General/html/index.html) is available under http://arm-software.github.io/CMSIS_5/General/html/index.html
 
 Use [Issues](https://github.com/ARM-software/CMSIS_5#issues-and-labels) to provide feedback and report problems for CMSIS Version 5. 
 

docs/Core/html/CMSIS_TZ_files.png

@@ -4,7 +4,7 @@
 <meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <meta http-equiv="X-UA-Compatible" content="IE=9"/>
 <title>Data Structures</title>
-<title>CMSIS-CORE: Data Structures</title>
+<title>CMSIS-Core (Cortex-M): Data Structures</title>
 <link href="tabs.css" rel="stylesheet" type="text/css"/>
 <link href="cmsis.css" rel="stylesheet" type="text/css" />
 <script type="text/javascript" src="jquery.js"></script>
@@ -31,10 +31,10 @@
  <tr style="height: 46px;">
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
-   <div id="projectname">CMSIS-CORE
-   &#160;<span id="projectnumber">Version 5.0.1</span>
+   <div id="projectname">CMSIS-Core (Cortex-M)
+   &#160;<span id="projectnumber">Version 5.0.2</span>
    </div>
-   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
  </tr>
  </tbody>
@@ -120,27 +120,28 @@
 <div class="textblock">Here are the data structures with brief descriptions:</div><div class="directory">
 <table class="directory">
 <tr id="row_0_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionAPSR__Type.html" target="_self">APSR_Type</a></td><td class="desc">Union type to access the Application Program Status Register (APSR) </td></tr>
-<tr id="row_1_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionCONTROL__Type.html" target="_self">CONTROL_Type</a></td><td class="desc">Union type to access the Control Registers (CONTROL) </td></tr>
-<tr id="row_2_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structCoreDebug__Type.html" target="_self">CoreDebug_Type</a></td><td class="desc">Structure type to access the Core Debug Register (CoreDebug) </td></tr>
-<tr id="row_3_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structDWT__Type.html" target="_self">DWT_Type</a></td><td class="desc">Structure type to access the Data Watchpoint and Trace Register (DWT) </td></tr>
-<tr id="row_4_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structFPU__Type.html" target="_self">FPU_Type</a></td><td class="desc">Structure type to access the Floating Point Unit (FPU) </td></tr>
-<tr id="row_5_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionIPSR__Type.html" target="_self">IPSR_Type</a></td><td class="desc">Union type to access the Interrupt Program Status Register (IPSR) </td></tr>
-<tr id="row_6_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structITM__Type.html" target="_self">ITM_Type</a></td><td class="desc">Structure type to access the Instrumentation Trace Macrocell Register (ITM) </td></tr>
-<tr id="row_7_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structMPU__Type.html" target="_self">MPU_Type</a></td><td class="desc">Structure type to access the Memory Protection Unit (MPU) </td></tr>
-<tr id="row_8_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structNVIC__Type.html" target="_self">NVIC_Type</a></td><td class="desc">Structure type to access the Nested Vectored Interrupt Controller (NVIC) </td></tr>
-<tr id="row_9_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSCB__Type.html" target="_self">SCB_Type</a></td><td class="desc">Structure type to access the System Control Block (SCB) </td></tr>
-<tr id="row_10_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSCnSCB__Type.html" target="_self">SCnSCB_Type</a></td><td class="desc">Structure type to access the System Control and ID Register not in the SCB </td></tr>
-<tr id="row_11_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSysTick__Type.html" target="_self">SysTick_Type</a></td><td class="desc">Structure type to access the System Timer (SysTick) </td></tr>
-<tr id="row_12_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structTPI__Type.html" target="_self">TPI_Type</a></td><td class="desc">Structure type to access the Trace Port Interface Register (TPI) </td></tr>
-<tr id="row_13_"><td class="entry"><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionxPSR__Type.html" target="_self">xPSR_Type</a></td><td class="desc">Union type to access the Special-Purpose Program Status Registers (xPSR) </td></tr>
+<tr id="row_1_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structARM__MPU__Region__t.html" target="_self">ARM_MPU_Region_t</a></td><td class="desc">Setup information of a single MPU Region </td></tr>
+<tr id="row_2_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionCONTROL__Type.html" target="_self">CONTROL_Type</a></td><td class="desc">Union type to access the Control Registers (CONTROL) </td></tr>
+<tr id="row_3_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structCoreDebug__Type.html" target="_self">CoreDebug_Type</a></td><td class="desc">Structure type to access the Core Debug Register (CoreDebug) </td></tr>
+<tr id="row_4_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structDWT__Type.html" target="_self">DWT_Type</a></td><td class="desc">Structure type to access the Data Watchpoint and Trace Register (DWT) </td></tr>
+<tr id="row_5_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structFPU__Type.html" target="_self">FPU_Type</a></td><td class="desc">Structure type to access the Floating Point Unit (FPU) </td></tr>
+<tr id="row_6_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionIPSR__Type.html" target="_self">IPSR_Type</a></td><td class="desc">Union type to access the Interrupt Program Status Register (IPSR) </td></tr>
+<tr id="row_7_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structITM__Type.html" target="_self">ITM_Type</a></td><td class="desc">Structure type to access the Instrumentation Trace Macrocell Register (ITM) </td></tr>
+<tr id="row_8_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structMPU__Type.html" target="_self">MPU_Type</a></td><td class="desc">Structure type to access the Memory Protection Unit (MPU) </td></tr>
+<tr id="row_9_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structNVIC__Type.html" target="_self">NVIC_Type</a></td><td class="desc">Structure type to access the Nested Vectored Interrupt Controller (NVIC) </td></tr>
+<tr id="row_10_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSCB__Type.html" target="_self">SCB_Type</a></td><td class="desc">Structure type to access the System Control Block (SCB) </td></tr>
+<tr id="row_11_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSCnSCB__Type.html" target="_self">SCnSCB_Type</a></td><td class="desc">Structure type to access the System Control and ID Register not in the SCB </td></tr>
+<tr id="row_12_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSysTick__Type.html" target="_self">SysTick_Type</a></td><td class="desc">Structure type to access the System Timer (SysTick) </td></tr>
+<tr id="row_13_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structTPI__Type.html" target="_self">TPI_Type</a></td><td class="desc">Structure type to access the Trace Port Interface Register (TPI) </td></tr>
+<tr id="row_14_" class="even"><td class="entry"><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionxPSR__Type.html" target="_self">xPSR_Type</a></td><td class="desc">Union type to access the Special-Purpose Program Status Registers (xPSR) </td></tr>
 </table>
 </div><!-- directory -->
 </div><!-- contents -->
 </div><!-- doc-content -->
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Feb 8 2017 10:20:41 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <li class="footer">Generated on Fri Aug 4 2017 14:04:11 for CMSIS-Core (Cortex-M) by ARM Ltd. All rights reserved.
 	<!--
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docs/Core/html/MemoryMap_NS.png

@@ -1,6 +1,7 @@
 var annotated =
 [
     [ "APSR_Type", "unionAPSR__Type.html", "unionAPSR__Type" ],
+    [ "ARM_MPU_Region_t", "structARM__MPU__Region__t.html", "structARM__MPU__Region__t" ],
     [ "CONTROL_Type", "unionCONTROL__Type.html", "unionCONTROL__Type" ],
     [ "CoreDebug_Type", "structCoreDebug__Type.html", "structCoreDebug__Type" ],
     [ "DWT_Type", "structDWT__Type.html", "structDWT__Type" ],